LTC4015_15 Datasheet, PDF (61/76 Pages) Linear Technology – Multichemistry Buck Battery Charger Controller with Digital Telemetry System

LTC4015
DETAILED Register Descriptions
QCOUNT_LO_ALERT_LIMIT (Sub-Address 0x10, Bits 15:0, R/W)
QCOUNT_HI_ALERT_LIMIT (Sub-Address 0x11, Bits 15:0, R/W)
These 16-bit words set and lower and upper limits on QCOUNT that can be used to trigger an SMBALERT when QCOUNT
falls below QCOUNT_LO_ALERT_LIMIT, or QCOUNT exceeds QCOUNT_HI_ALERT_LIMIT. The values use the same
format as QCOUNT.
QCOUNT_PRESCALE_FACTOR (Sub-Address 0x12, Bits 15:0, R/W)
This 16-bit word along with R_SNSB is used to set the q_LSB value of Coulomb counter accumulator, QCOUNT.
q_LSB
=
QCOUNT_PRESCALE_FACTOR
8333.33 •R_SNSB
A
•
s(COULOMBS)
QCOUNT (Sub-Address 0x13, Bits 15:0, R/W)
This 16-bit word reports the current value of Coulomb counter accumulator, QCOUNT. This register can be written to
represent a known state of charge of the battery.
q_LSB
=
QCOUNT_PRESCALE_FACTOR
8333.33 •R_SNSB
A
•
s(COULOMBS)
CONFIG_BITS (Sub-Address 0x14, Bits 8:0, R/W)
This register consists of individual system configuration bits which control various features of the LTC4015.
suspend_charger (Sub-Address 0x14, Bit 8, R/W)
Setting this bit causes battery charging to be suspended, and forces charger_suspended=1. A new battery charge
cycle can be forced by setting and then resetting suspend_charger.
run_bsr (Sub-Address 0x14, Bit 5, R/W)
Setting this bit causes a single battery series resistance (BSR) measurement to be made by the LTC4015. Once
the series resistance measurement is complete, the LTC4015 resets the run_bsr bit to 0, and the result is reported
as BSR. ICHARGE_BSR is the value of IBAT that was used in the BSR calculation. See the section Battery Series
Resistance Measurement.
force_meas_sys_on (Sub-Address 0x14, Bit 4, R/W)
Setting this bit causes the A/D measurement system to operate at all times, including when input power is unavailable
(vin_gt_vbat=0). This feature is disabled by default in order to reduce battery-only load current. Setting this bit has
the advantage of maintaining up-to-date system data, but will increase battery drain.
When input power is absent, the measurement system can be sampled periodically to reduce quiescent current.
See the Measurement Subsystem description for details.
mppt_en_i2c (Sub-Address 0x14, Bit 3, R/W)
Setting this bit causes the maximum power point tracking algorithm to run when the switching charger is active.
The maximum power point algorithm uses the UVCL regulation loop to seek the optimum power point for resistive
sources such as a solar panel. See the section maximum power point tracking for more information. The maximum
power point algorithm can also be enabled by connecting the MPPT pin to the VCC2P5 pin.
en_qcount (Sub-Address 0x14, Bit 2, R/W)
Setting this bit enables the LTC4015 Coulomb counter. This feature is disabled by default to reduce quiescent current.
For more information www.linear.com/LTC4015
4015f
61