LTC4015_15 Datasheet, PDF (46/76 Pages) Linear Technology – Multichemistry Buck Battery Charger Controller with Digital Telemetry System

LTC4015
Applications Information
20 times that of the total input capacitance of the top
MOSFET. The bypass capacitor on DRV_CC should be at
least 10 times the value of C_B.
With the top MOSFET on, the boost voltage is above the
system supply rail: V_BOOST = V_SYS + V_DRVCC.
The reverse break down of the external diode, D_B, must
be greater than V_SYS(MAX) + V_DRVCC(MAX).
D_B can be either a Schottky diode or a fast switching PN
diode. Care must be taken to not exceed the maximum
BOOST-SW voltage of 5.5V which may be possible with a
Schottky under certain conditions, particularly if the step
down charger is operating asynchronously. Fast switching
PN diodes are recommended due to their low leakage and
junction capacitance.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time dura-
tion that the LTC4015 is capable of turning on the top
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. The
minimum on-time for the LTC4015 is approximately 85ns.
Low duty cycle applications may approach this minimum
on-time limit. If the duty cycle falls below what can be
accommodated by the minimum on-time, the controller
will begin to skip cycles. The V_BAT voltage will continue
to be regulated, but the ripple voltage and current will
increase. If cycling skipping is undesirable care should
be taken to ensure that:
withstand the maximum voltage on V_BAT while the V_DSS
of output ideal diode MOSFET must withstand the high-
est voltage on V_IN. The gate drive for both ideal diodes is
5V. This requires the use of logic-level threshold P and
N-channel MOSFETs. As a general rule, select MOSFETs
with a low enough R_DS(ON) to obtain the desired V_DS while
operating at full load current. The LTC4015 will regulate
the forward voltage drop across the input and output ideal
diode MOSFETs at 15mV if R_DS(ON) is low enough. The
required R_DS(ON) can be calculated by dividing 15mV by
the load current in amps.
Achieving forward regulation will minimize power loss and
heat dissipation, but it is not a necessity. If a forward volt-
age drop of more than 15mV is acceptable then a smaller
MOSFET can be used, but must be sized compatible with
the higher power dissipation. Care should be taken to
ensure that the power dissipated is never allowed to rise
above the manufacturer’s recommended maximum level.
UVCLFB Resistor Divider Selection
The LTC4015 input undervoltage current limit (UVCL)
function regulates voltage at the UVCLFB pin based on
the value programmed in the UVCLFB_SETTING register.
Do not write to the VIN_UVCL_SETTING register when
MPPT is enabled.
If MPPT is enabled, the UVCLFB input voltage resistor
divider should be set to 10kΩ and 294kΩ for the bottom
and top resistors, respectively. Resistor tolerance should
be ±1% or better.
V_BAT
V_SYS • f_SW
>
t_ON(MIN)
=
85ns
Ideal Diode MOSFET Selection
An external N-channel MOSFET is required for the input
ideal diode and a P-channel MOSFET for output ideal diode.
Important parameters for the selection of these MOSFETs
are the maximum drain-source voltage, V_DSS, gate thresh-
old voltage and on-resistance (R_DS(ON)). When the input
is grounded the battery stack voltage is applied across the
input ideal diode MOSFET. When V_BAT is at 0V, the input
voltage is applied across the output ideal diode MOSFET.
Therefore, the V_DSS of the input ideal diode MOSFET must
If maximum power point tracking (MPPT) is not enabled,
the default undervoltage setting of VIN_UVCL_SETTING =
0xFF sets the UVCLFB undervoltage servo level to 1.2V.
In this case, the input voltage resistor divider should be
chosen such that UVCLFB = 1.2V when V_IN is slightly above
the higher of 4.3V or V_BAT(MAX), to prevent undervoltage
lockout (UVLO). For example, for a two cell Li-Ion applica-
tion, the bottom and top resistors in the UVCLFB divider
could be chosen as 75kΩ and 470kΩ, respectively, which
sets the input undervoltage regulation limit at 8.72V.
To disable the undervoltage regulation feature, the UVCLFB
pin can be tied to V_IN through a 1MΩ resistor (in effect,
omitting the bottom resistor of the UVCLFB input voltage
divider). When a UVCLFB input voltage resistor divider
4015f
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