LTC4015_15 Datasheet, PDF (47/76 Pages) Linear Technology – Multichemistry Buck Battery Charger Controller with Digital Telemetry System

LTC4015
Applications Information
is present, if maximum power point tracking is disabled,
input undervoltage regulation can be prevented by setting
VIN_UVCL_SETTING to its lowest value (0x00).
UVCL and MPPT When Available Input Power is Low
The LTC4015 battery charger function requires a minimum
amount of current to operate, which varies depending on the
application (switching MOSFET selection, compensation,
etc). If the maximum input current available from the V_IN
supply is above 2mA to 3mA but below the minimum level
required to operate the charger (generally approximately
in the range 5mA to 20mA) then the battery may
actually be discharged slightly by the charger. Under
these conditions—for example, a very dimly lit (but not
completely dark) solar panel—the worst-case battery
drain current is generally less than 10mA, and persists
only as long as the available input current from the V_IN
source remains in this range. If the available input current
falls to below 2mA to 3mA, then the battery discharge
returns to near normal battery only mode levels. As
such, if the input source is a solar panel, this battery
drain will generally be short-lived and infrequent enough
(for example, for a brief period shortly before sunrise and
after sunset) as to be insignificant. However, if this drain
is a concern, it can be mitigated by disabling the charger
(setting suspend_charger=1) whenever I_CHG falls below
1% of full-scale (IBAT <= 218), and retrying (writing
suspend_charger=0) periodically (e.g. every 60 seconds).
Optionally, this retry can be limited to only occur when
V_IN is above a known good threshold.
PCB Layout Considerations
When laying out the printed circuit board, the following
guidelines should be used to ensure proper operation of
the IC. Check the following in your layout:
1. Keep M1, M2, D1, D2 and C_SYS close together. The high
dI/dt loop formed by the MOSFETs, Schottky diodes and
C_SYS shown in Figure 13 should have short wide traces
to minimize high frequency noise and voltage stress
from inductive ringing. Surface mount components
are preferred to reduce parasitic inductances from
component leads. Connect the drain of the top MOSFET
and cathode of the top diode directly to the positive
terminal of C_SYS. Connect the source of the bottom
MOSFET and anode of the bottom diode directly to the
negative terminal of C_SYS. This capacitor provides the
AC current to the MOSFETs.
2. GND is referenced to the negative terminal of the V_BAT
decoupling capacitor. The negative terminal of C_SYS
should be as close as possible to negative terminal of
C_BAT by placing the capacitors next to each other and
away from the switching loop described above. The
combined IC ground pin/paddle and the ground return
of C_INTVCC and C_DRVCC must return to the combined
negative terminals of C_SYS and C_BAT.
3. Effective grounding techniques are critical for success-
ful DC/DC converter layouts. Orient power components
such that switching current paths in the ground plane do
not cross through the GND pin and exposed pad on the
backside of the LTC4015. Switch path currents can be
controlled by orienting the MOSFET switches, Schottky
diodes, the inductor, and V_SYS and V_BAT decoupling
capacitors in close proximity to each other.
4. Route CSP and CSN sense lines together, keep them
short. Place a 1nF ceramic capacitor across CSP-CSN
as close as possible to the LTC4015. Filter components
should be placed near the part and not near sense
resistor. Ensure accurate current sensing with Kelvin
connections at the sense resistors. See Figure 14.
5. Route CLP and CLN sense lines together, keep them
short. Filter components should be placed near the part
and not near sense resistor. Ensure accurate current
sensing with Kelvin connections at the sense resistors.
See Figure 15.
6. Locate the DRV_CC and BOOST decoupling capacitors
in close proximity to the IC. These capacitors carry the
MOSFET drivers’ high peak currents. An additional 0.1μF
ceramic capacitor placed immediately next to the DRV_CC
pin can help improve noise performance substantially.
7. Locate the small signal components away from high
frequency switching nodes (BOOST, SW, TG, and BG). All
of these nodes have very large and fast moving signals
and therefore should be kept on the output side of the
LTC4015.
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