LTC4015_15 Datasheet, PDF (45/76 Pages) Linear Technology – Multichemistry Buck Battery Charger Controller with Digital Telemetry System

LTC4015
Applications Information
Power MOSFET Selection
Two external power MOSFETs must be selected for the
LTC4015’s synchronous controller: one N-channel MOS-
FET for the top switch and one N-channel MOSFET for
the bottom switch. The selection criteria of the external
N-channel power MOSFETs include maximum drain-
source voltage (V_DSS), threshold voltage, on-resistance
(R_DS(ON)), reverse transfer capacitance (C_RSS), total gate
charge (Q_G) and maximum continuous drain current.
V_DSS should be selected to be higher than the maxi-
mum input supply voltage (including transient) for both
MOSFETs. The peak-to-peak drive levels are set by the
DRV_CC voltage. Logic-level threshold MOSFETs must be
used because DRV_CC is powered from either INTV_CC (5V)
or an external LDO whose output voltage must be less than
5.5V. MOSFET power losses are determined by R_DS(ON)
and C_RSS and Q_G.
The conduction loss at maximum charge current for the
top MOSFET switches are:
P_COND(TOP)
=


V_BAT
V_SYS
•I_CHG(MAX)2
•R_DS(ON)^{}
(1+ δΔT )
P_COND(BOT)
=


_1–
V_BAT
V_SYS


I_CHG(MAX)2
•R_DS(ON)^{}
(1+
δΔT)
Another power loss related to switching MOSFET selection
is the power lost to driving the gates. The total gate charge,
Q_G, must be charged and discharged each switching cycle.
The power is lost to the internal LDO and gate drivers within
the LTC4015. The power lost due to charging the gates is:
PG = (Q_GTOP + Q_GBOT) • f_SW • V_SYS
Schottky Diode Selection
Optional Schottky diodes can be placed in parallel with the
top and bottom MOSFET switches. These diodes clamp
SW during the non-overlap times between conduction of
the top and bottom MOSFET switches. This prevents the
body diodes of the MOSFET switches from turning on,
storing charge during the non-overlap time and requir-
ing a reverse recovery period that could cost as much as
3% in efficiency at high V_IN. One or both diodes can be
omitted if the efficiency loss can be tolerated. The diode
can be rated for about one-half to one-fifth of the full load
current since it is on for only a fraction of the duty cycle.
Larger diodes result in additional switching losses due to
their larger junction capacitance. In order for the diodes
to be effective, the inductance between them and the top
and bottom MOSFETs must be as small as possible. This
mandates that these components be placed next to each
other on the same layer of the PC board.
The term (1+ δ∆T) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs Temperature curve, but δ
= 0.005/°C can be used as an approximation for low voltage
MOSFETs. Both MOSFET switches have conduction loss .
However, transition loss occurs only in the top MOSFET
in step-down converter. This loss is proportional to V_SYS2
and can be considerably larger in high voltage applications
(V_SYS > 20V). The maximum transition loss is:
P_TRAN = k/2 • (V_SYS)² • I_CHG(MAX) • C_RSS • f_SW
where k is related to the drive current during the Miller
plateau and is approximately equal to one.
Choosing a high side MOSFET that has a higher R_DS(ON)
and lower CRSS can minimize overall losses; by reducing
transition losses more than the corresponding conduction
loss increase.
Top MOSFET Driver Supply (C_B, D_B)
An external bootstrap capacitor, C_B, connected to the
BOOST pin supplies the gate drive voltage for the top
MOSFET. Capacitor C_B in Figure 12 is charged though
external diode, D_B, from DRV_CC when the SW pin is low.
The value of the bootstrap capacitor, C_B, needs to be
BOOST
LTC4015
SW
DRV_CC
C_B
0.1µF
D_B
> 2.2µF
INTV_CC
1µF
4015 F12
Figure 12. Bootstrap Capacitor/Diode and DRV_CC Connections
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4015f
45