LTC4015_15 Datasheet, PDF (41/76 Pages) Linear Technology – Multichemistry Buck Battery Charger Controller with Digital Telemetry System

LTC4015
Operation
Step Down Switching Charger Controller
The LTC4015’s primary power path is a fully synchronous
step down switching charger controller. Due to its all NMOS
design, a diode and capacitor are required to provide high
side boosted drive. Taking error signals from four control
loops simultaneously, the feedback paths are externally
compensated with a RC network connected to the V_C pin.
The switching controller is designed to charge single or
multiple batteries. Normal charging proceeds at a constant-
current until the batteries reach their target voltage. The
maximum charge current is determined by the value of
the sense resistor, R_SNSB, used in series with the inductor.
The charge current loop servos the voltage across R_SNSB
to the value determined by ICHARGE_DAC.
When charging is enabled an internal soft-start will ramp
up the charge current from zero to ICHARGE_TARGET.
Both the battery voltage and charge current can be read
back over I²C. The LTC4015 provides constant power
charging by limiting input current drawn by the switching
controller. The input current limit will reduce charge
current to limit the voltage across the input sense resistor,
R_SNSI, to IIN_LIMIT_SETTING. If the combined system
load plus battery charge current is large enough to cause
the switching controller to reach the programmed input
current limit, the input current limit loop will reduce the
charge current. Even if the charge current is programmed
to exceed the allowable input current, the input current
will not be violated; the charger will reduce its current
as needed. The input current can be read back over I²C.
DRV_CC
The bottom gate driver is powered from the DRV_CC pin.
DRV_CC is normally connected to the INTV_CC pin. An external
LDO or DC/DC converter can also be used to power the
top and bottom gate driver to minimize power dissipa-
tion inside the IC. The use of a DC/DC for DRV_CC can also
minimize power dissipation in general.
INTV_CC/DRV_CC and IC Power Dissipation
The LTC4015 features an internal PMOS low dropout linear
regulator (LDO) that supplies power to INTV_CC from V_SYS.
INTV_CC powers the gate drivers (when DRV_CC is connected
to INTV_CC) and much of the LTC4015’s internal circuitry.
The INTV_CC LDO regulates the voltage at the INTV_CC pin
to 5V. The LDO can supply a maximum current of 50mA
and must be bypassed to ground with a ceramic capacitor
with a minimum value of 4.7μF. If DRV_CC is not connected
to INTV_CC, it should have at least a 2.2μF ceramic or low
ESR electrolytic capacitor. No matter what type of bulk
capacitor is used on DRV_CC, an additional 0.1μF ceramic
capacitor placed directly adjacent to the DRV_CC pin and
GND is highly recommended. Good bypassing is needed
to supply the high transient currents required by the
MOSFET gate drivers. High input voltage applications in
which large MOSFETs are being driven at high frequencies
may cause the maximum junction temperature rating for
the LTC4015 to be exceeded. The DRV_CC current, which
is dominated by the gate charge current, is supplied by
the INTV_CC LDO. Power dissipation for the IC in this case
is highest and is approximately equal to (V_SYS) • (I_Q + I_G),
where I_Q is the non-switching quiescent current of ~4mA
and I_G is gate charge current. The junction temperature can
be estimated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the I_G supplied by
the INTV_CC LDO is limited to less than 42mA from a 35V
supply in the QFN package at a 70°C ambient temperature:
T_J = 70°C + (35V)(4mA + 42mA)(34°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the DRV_CC current must be checked while oper-
ating in continuous conduction mode at maximum V_SYS.
The power dissipation in the IC is significantly reduced if
DRV_CC is powered from an external LDO. In this case the
power dissipation in the IC is equal to power dissipation
due to I_Q and the power dissipated in the gate drivers,
(VDRV_CC) • (I_G). Assuming the external DRV_CC LDO out-
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