LTC3875_15 Datasheet, PDF (33/44 Pages) Linear Technology – Dual, 2-Phase, Synchronous Controller with Low Value DCR Sensing and Temperature Compensation

LTC3875
Applications Information
8. Use a low impedance source such as a logic gate to
drive the MODE/PLLIN pin and keep the lead as short
as possible.
9. The 47pF to 330pF ceramic capacitor between the ITH
pin and signal ground should be placed as close as
possible to the IC. Figure 15 illustrates all branch cur-
rents in a switching regulator. It becomes very clear
after studying the current waveforms why it is critical to
keep the high switching current paths to a small physical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a com-
mon ground path with any switched current paths. The
left half of the circuit gives rise to the noise generated
by a switching regulator. The ground terminations of
the synchronous MOSFET and Schottky diode should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP^® compensa-
tion allows overcompensation for PC layouts which are
not optimized but this is not the recommended design
procedure.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the
input voltage range down to dropout and until the output
load drops below the low current operation threshold—
typically 10% of the maximum designed current level in
Burst Mode^® operation. The duty cycle percentage should
be maintained from cycle to cycle in a well-designed, low
noise PCB implementation. Variation in the duty cycle at a
sub-harmonic rate can suggest noise pickup at the current
or voltage sensing inputs or inadequate loop compensa-
tion. Overcompensation of the loop can be used to tame
a poor PC layout if regulator bandwidth optimization is
not required. Only after each controller is checked for
its individual performance should both controllers be
turned on at the same time. A particularly difficult region
of operation is when one controller channel is nearing its
current comparator trip point when the other channel is
turning on its top MOSFET. This occurs around 50% duty
cycle on either channel due to the phasing of the internal
clocks and may cause minor duty cycle jitter.
Reduce V_IN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering V_IN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C_IN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
Design Example
As a design example for a single output dual phase high
current regulator, assume V_IN = 12V(nominal), V_IN = 20V
(maximum), V_OUT = 1.5V, I_MAX1,2 = 30A, and f = 400kHz
(see Figure 16).
The regulated output voltages are determined by:
V_OUT
=
0.6
•


1+
R_B
R_A


Shorting the V_OSNS1+ pins and V_OSNS2+ pins together. Us-
ing 20k, 1% resistor from V_OSNS+ node to remote ground,
the top feedback resistor is (to the nearest 1% standard
value) 30.1k.
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