LTC3875_15 Datasheet, PDF (29/44 Pages) Linear Technology – Dual, 2-Phase, Synchronous Controller with Low Value DCR Sensing and Temperature Compensation

LTC3875
Applications Information
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
FREQ PIN VOLTAGE (V)
3875 F12
Figure 12. Relationship Between Oscillator Frequency
and Voltage at the FREQ Pin
2.4V 5V
10µA
R_SET
EXTERNAL
OSCILLATOR
MODE/
PLLIN
DIGITAL
PHASE/ SYNC
FREQUENCY
DETECTOR
FREQ
VCO
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
( ) ^{tON(MIN) <}
V_OUT
V_IN • f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated, but
the ripple voltage and current will increase. The minimum
on-time for the LTC3875 is approximately 90ns, with rea-
sonably good PCB layout, minimum 30% inductor current
ripple and at least 2mV ripple on the current sense signal
or equivalent 10mV between SNSA⁺ and SNS^– pins. The
minimum on-time can be affected by PCB switching noise
in the voltage and current loop. As the peak sense voltage
decreases the minimum on-time gradually increases to
110ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Efficiency Considerations
3875 F13
Figure 13. Phase-Locked Loop Block Diagram
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
Typically, the external clock (on MODE/PLLIN pin) input
high threshold is 1.6V, while the input low threshold is 1V.
It is not recommended to apply the external clock when
IC is in shutdown.
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3875 circuits: 1) IC V_IN current, 2) INTV_CC
regulator current, 3) I²R losses, 4) Topside MOSFET
transition losses.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the LTC3875 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
1. The V_IN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. V_IN current typically results
in a small (<0.1%) loss.
3875fa
For more information www.linear.com/LTC3875
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