LTC3875_15 Datasheet, PDF (12/44 Pages) Linear Technology – Dual, 2-Phase, Synchronous Controller with Low Value DCR Sensing and Temperature Compensation

LTC3875
Operation
to the error amplifier. The V_FB signal is regulated to the
lower of the error amplifier’s three noninverting inputs
(the internal soft-start ramp, the TK/SS pin or the internal
600mV reference). As the ramp voltage rises from 0V to
0.6V, over approximately 600µs, the output voltage rises
smoothly from its pre-biased value to its final set value.
Certain applications can require the start-up of the con-
verter into a non-zero load voltage, where residual charge
is stored on the output capacitor at the onset of converter
switching. In order to prevent the output from discharging
under these conditions, the top and bottom MOSFETs are
disabled until soft-start is greater than V_FB.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
The LTC3875 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode,
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to a DC
voltage below 0.6V (e.g., SGND). To select pulse-skipping
mode of operation, tie the MODE/PLLIN pin to INTV_CC. To
select Burst Mode operation, float the MODE/PLLIN pin.
When a controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though the
voltage on the I_TH pin indicates a lower value. If the aver-
age inductor current is higher than the load current, the
error amplifier, EA, will decrease the voltage on the I_TH
pin. When the I_TH voltage drops below 0.5V, the internal
sleep signal goes high (enabling sleep mode) and both
external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
(I_REV) turns off the bottom external MOSFET just before
the inductor current reaches zero, preventing it from re-
versing and going negative. Thus, the controller operates
in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the I_TH pin. In this mode, the efficiency at
light loads is lower than in Burst Mode operation. However,
continuous mode has the advantages of lower output ripple
and less interference with audio circuitry.
When the MODE/PLLIN pin is connected to INTV_CC, the
LTC3875 operates in PWM pulse-skipping mode at light
loads. At very light loads, the current comparator, I_CMP,
may remain tripped for several cycles and force the external
top MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Multichip Operations (PHASMD and CLKOUT Pins)
The PHASMD pin determines the relative phases between
the internal channels as well as the CLKOUT signal as shown
in Table 1. The phases tabulated are relative to zero phase
being defined as the rising edge of the clock of phase 1.
Table 1
PHASMD
Phase 1
Phase 2
CLKOUT
GND
FLOAT
INTV_CC
0°
0°
0°
180°
180°
240°
60°
90°
120°
The CLKOUT signal can be used to synchronize additional
power stages in a multiphase power supply solution feeding
a single, high current output or separate outputs. Input
capacitance ESR requirements and efficiency losses are
substantially reduced because the peak current drawn from
the input capacitor is effectively divided by the number of
phases used and power loss is proportional to the RMS
current squared. A 2-stage, single output voltage imple-
mentation can reduce input path power loss by 75% and
radically reduce the required RMS current rating of the
input capacitor(s).
3875fa
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