LTC3875_15 Datasheet, PDF (27/44 Pages) Linear Technology – Dual, 2-Phase, Synchronous Controller with Low Value DCR Sensing and Temperature Compensation

LTC3875
Applications Information
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value.
The out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (V_OUT)/(V_IN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
( )( ) ^C_IN
Required I_RMS
≈
I_MAX
V_IN

V_OUT
V_IN – V_OUT ^1/2
This formula has a maximum at V_IN = 2V_OUT, where
I_RMS = I_OUT/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3875, ceramic capacitors
can also be used for C_IN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3875 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The sources of the top MOSFETs
should be placed within 1cm of each other and share a
common C_IN(s). Separating the sources and C_IN may pro-
duce undesirable voltage and current resonances at V_IN.
A small (0.1µF to 1µF) bypass capacitor between the chip
V_IN pin and ground, placed close to the LTC3875, is also
suggested. A 2.2Ω to 10Ω resistor placed between C_IN
and the V_IN pin provides further isolation between the
two channels.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆V_OUT) is approximated by:
∆V_OUT
≈ I_RIPPLE


ESR +
1
8fC_OUT


where f is the operating frequency, C_OUT is the output
capacitance and I_RIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I_RIPPLE increases with input voltage.
Setting Output Voltage
The LTC3875 output voltages are each set by an external
feedback resistive divider carefully placed across the out-
put, as shown in Figure 1. The regulated output voltage
is determined by:
V_OUT
=
0.6V
•


1+
R_D1
R_D2


To improve the frequency response, a feed-forward ca-
pacitor, C_FF, may be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
Fault Conditions: Current Limit and Current Foldback
The LTC3875 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
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