LTC3875_15 Datasheet, PDF (28/44 Pages) Linear Technology – Dual, 2-Phase, Synchronous Controller with Low Value DCR Sensing and Temperature Compensation

LTC3875
Applications Information
with very low duty cycles, the LTC3875 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short-
circuit ripple current is determined by the minimum
on-time, t_ON(MIN), of the LTC3875 (≈90ns), the input volt-
age and inductor value:
∆I_L(SC)
=
t_ON(MIN)
•
V_IN
L
The resulting short-circuit current is:
I_SC
=
1/
3 V_SENSE(MAX)
R_SENSE
–
1
2
∆I_L(SC)
Overcurrent Fault Recovery
When the output of the power supply is loaded beyond its
preset current limit, the regulated output voltage will col-
lapse depending on the load. The output may be shorted
to ground through a very low impedance path or it may
be a resistive short, in which case the output will collapse
partially, until the load current equals the preset current
limit. The controller will continue to source current into
the short. The amount of current sourced depends on
the ILIM pin setting and the V_FB voltage as shown in the
Current Foldback graph in the Typical Performance Char-
acteristics section. Upon removal of the short, the output
soft starts using the internal soft-start, thus reducing
output overshoot. In the absence of this feature, the output
capacitors would have been charged at current limit, and
in applications with minimal output capacitance this may
have resulted in output overshoot. Current limit foldback
is not disabled during an overcurrent recovery. The load
must step below the folded back current limit threshold
in order to restart from a hard short.
The internal thermal shutdown is set for approximately
160°C with 10°C of hysteresis. When the chip reaches
160°C, both TG and BG are disabled until the chip cools
down below 150°C.
Phase-Locked Loop and Frequency Synchronization
The LTC3875 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (V_CO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180° out-of-phase
with the external clock. The phase detector is an edge
sensitive digital type that provides zero degrees phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics
of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter
network. There is a precision 10µA of current flowing out
of FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clock is applied to the MODE/PLLIN pin. The internal switch
between FREQ pin and the integrated PLL filter network
is on, allowing the filter network to be precharged to the
same voltage potential as the FREQ pin. The relationship
between the voltage on the FREQ pin and the operating
frequency is shown in Figure 12 and specified in the Electri-
cal Characteristic table. If an external clock is detected on
the MODE/PLLIN pin, the internal switch mentioned above
will turn off and isolate the influence of FREQ pin. Note
that the LTC3875 can only be synchronized to an external
clock whose frequency is within range of the LTC3875’s
internal V_CO. This is guaranteed to be between 250kHz and
720kHz. A simplified block diagram is shown in Figure 13.
Thermal Protection
Excessive ambient temperatures, loads and inadequate
airflow or heat sinking can subject the chip, inductor,
FETs etc. to high temperatures. This thermal stress re-
duces component life and if severe enough, can result
in immediate catastrophic failure (Note 1). To protect the
power supply from undue thermal stress, the LTC3875
has a fixed chip temperature-based thermal shutdown.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f_OSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
3875fa
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