LTC3875_15 Datasheet, PDF (31/44 Pages) Linear Technology – Dual, 2-Phase, Synchronous Controller with Low Value DCR Sensing and Temperature Compensation

LTC3875
Applications Information
a power MOSFET directly across the output capacitor and
driving the gate with an appropriate signal generator is a
practical way to produce a realistic load-step condition. The
initial output voltage step resulting from the step change
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the I_TH pin
signal which is in the feedback loop and is the filtered and
compensated control loop response. The gain of the loop
will be increased by increasing R_C and the bandwidth of the
loop will be increased by decreasing C_C. If R_C is increased
by the same factor that C_C is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C_LOAD to C_OUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C_LOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 14. Figure 15 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located within
1cm of each other with a common drain connection at
C_IN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C_INTVCC must return to the combined C_OUT (–)
terminals. The V_FB and I_TH traces should be as short
as possible. The path formed by the top N-channel
MOSFET, Schottky diode and the C_IN capacitor should
have short leads and PC trace lengths. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the Schottky loop described above.
3. Are the SNSD⁺, SNSA⁺ and SNS^– printed circuit traces
routed together with minimum PC trace spacing? The
filter capacitors between SNSD⁺, SNSA⁺ and SNS^–
should be as close as possible to the pins of the IC.
Connect the SNSD⁺ and SNSA⁺ pins to the filter resistors
as illustrated in Figure 4.
4. Do the (+) plates of C_IN connect to the drain of the
topside MOSFET as closely as possible? This capacitor
provides the pulsed current to the MOSFET.
5. Keep the switching nodes, SW, BOOST and TG away
from sensitive small-signal nodes (SNSD⁺, SNSA⁺,
SNS^–, V_OSNS+, V_OSNS–). Ideally the SW, BOOST and
TG printed circuit traces should be routed away and
separated from the IC and especially the quiet side of
the IC. Separate the high dv/dt traces from sensitive
small-signal nodes with ground traces or ground planes.
6. The INTV_CC decoupling capacitor should be placed im-
mediately adjacent to the IC between the INTV_CC pin
and PGND plane. A 1µF ceramic capacitor of the X7R
or X5R type is small enough to fit very close to the IC
to minimize the ill effects of the large current pulses
drawn to drive the bottom MOSFETs. An additional
4.7µF to 10µF of ceramic, tantalum or other very low
ESR capacitance is recommended in order to keep the
internal IC supply quiet.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
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