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LTC3864 Datasheet, PDF (3/28 Pages) Linear Technology – 60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability
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LTC3864
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Input Supply
VIN
VUVLO
Input Voltage Operating Range
Undervoltage Lockout
3.5
60
V
(VIN-VCAP) Ramping Up Threshold
l 3.25 3.50
3.8
V
(VIN-VCAP) Ramping Down Threshold
l 3.00 3.25 3.50
V
Hysteresis
0.25
V
IQ
Input DC Supply Current
Pulse-Skipping Mode
Burst Mode Operation
Shutdown Supply Current
PLLIN/MODE = 0V, FREQ = 0V,
VFB = 0.83V (No Load)
PLLIN/MODE = Open, FREQ = 0V,
VFB = 0.83V (No Load)
RUN = 0V
0.77
1.2
mA
40
60
µA
7
12
µA
Output Sensing
VREG
Regulated Feedback Voltage
∆VREG
∆VIN
Feedback Voltage Line Regulation
∆VREG
∆VITH
Feedback Voltage Load Regulation
gm(EA)
Error Amplifier Transconductance
IFB
Feedback Input Bias Current
Current Sensing
VITH = 1.2V (Note 5)
VIN = 3.8V to 60V (Note 5)
VITH = 0.6V to 1.8V (Note 5)
VITH = 1.2V, ∆IITH = ±5µA (Note 5)
l 0.792 0.800 0.809
V
–0.005
0.005
%/V
–0.1 –0.015 0.1
%
1.8
mS
–50
–10
50
nA
VILIM
Current Limit Threshold (VIN-VSENSE)
ISENSE
SENSE Pin Input Current
Start-Up and Shutdown
VFB = 0.77V
VSENSE = VIN
l 85
95
103
mV
0.1
2
µA
VRUN
RUN Pin Enable Threshold
VRUNHYS RUN Pin Hysteresis
ISS
Soft-Start Pin Charging Current
Switching Frequency and Clock Synchronization
VRUN Rising
VSS = 0V
l 1.22 1.26 1.32
V
150
mV
10
µA
f
Programmable Switching Frequency
fLO
fHI
fSYNC
VCLK(IH)
VCLK(LO)
fFOLD
Low Switching Frequency
High Switching Frequency
Synchronization Frequency
Clock Input High Level into PLLIN/MODE
Clock Input Low Level into PLLIN/MODE
Foldback Frequency as Percentage of
Programmable Frequency
RFREQ = 24.9kΩ
RFREQ = 64.9kΩ
RFREQ = 105kΩ
FREQ = 0V
FREQ = Open
VFB = 0V, VFREQ = 0
105
kHz
375
440
505
kHz
810
kHz
320
350
380
kHz
485
535
585
kHz
l 75
750
kHz
l
2
V
l
0.5
V
18
%
tON(MIN) Minimum On-Time
Gate Driver
220
ns
VCAP
Gate Bias LDO Output Voltage (VIN-VCAP)
VCAPDROP Gate Bias LDO Dropout Voltage
∆VCAP(LINE) Gate Bias LDO Line Regulation
∆VCAP(LOAD) Gate Bias LDO Load Regulation
IGATE = 0mA
VIN = 5V, IGATE = 15mA
9V ≤ VIN ≤ 60V, IGATE = 0mA
Load = 0mA to 20mA
l 7.6
8.0
8.5
V
0.2
0.5
V
0.002 0.03
%/V
–3.5
%
3864f
3
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