LTC3864 Datasheet, PDF (26/28 Pages) Linear Technology – 60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability

LTC3864
TYPICAL APPLICATIONS
12V to 58V Input, 12V/2A Output at 535kHz
C_CAP
0.1µF
CAP
RUN
V_IN
MODE/PLLN
SENSE
C_IN2 ⁺
4.7µF
V_IN
C_IN1 ^{12V TO 58V}
33µF
63V
C_VIN
0.1µF
R_SENSE
30mΩ
C_ITH1
3300pF
R_ITH 11.3k
C_ITH2 100pF
SS
GATE
LTC3864
ITH
FREQ
SGND
PGOOD
V_FB
PGND
MP L1
22µH
D1
C_IN1: SANYO 63ME33AX
D1: DIODES INC SBR3U100LP
L1: TOKO 1217AS-H-220M
MP: VISHAY/SILICONIX SI7465DP
*V_OUT FOLLOWS V_IN WHEN 3.5V ≤ V_IN ≤ 12V
R_PGD2
549k
R_FB2
845k
10µF
×2
V_OUT*
12V
2A
R_PGD1
402k
R_FB1
60.4k
3864 TA04a
Efficiency
90
Burst Mode
OPERATION
80
70
60
50
0.01
PULSE-SKIPPING
V_IN = 48V
V_OUT = 12V
0.1
1
LOAD CURRENT (A)
3864 TA04b
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
0.70 ±0.05
4.00 ±0.10
(2 SIDES)
3.60 ±0.05
2.20 ±0.05
3.30 ±0.05
1.70 ± 0.05
PACKAGE
OUTLINE
PIN 1
TOP MARK
(NOTE 6)
0.25 ± 0.05
0.50 BSC
2.50 REF
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
26
R = 0.05
TYP
3.00 ±0.10
(2 SIDES)
0.75 ±0.05
0.00 – 0.05
R = 0.115
7
TYP
0.40 ± 0.10
12
3.30 ±0.10
1.70 ± 0.10
6
0.25 ± 0.05
2.50 REF
1
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0806 REV D
3864f