LTC3864 Datasheet, PDF (11/28 Pages) Linear Technology – 60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability

LTC3864
OPERATION
the internal sleep signal goes high, enabling sleep mode.
The ITH pin is then disconnected from the output of the
error amplifier and held at 0.45V.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current to 40µA while the load
current is supplied by the output capacitor. As the output
voltage and hence the feedback voltage decreases, the
error amplifier’s output will rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the error amplifier, the sleep signal goes low, and the
controller resumes normal operation by turning on the
external P-MOSFET on the next cycle of the internal oscil-
lator. In Burst Mode operation, the peak inductor current
has to reach at least 25% of current limit for the current
comparator, ICMP, to trip and turn the P-MOSFET back off,
even though the ITH voltage may indicate a lower current
setpoint value.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3864 will skip pulses during light loads. In
this mode, ICMP may remain tripped for several cycles and
force the external MOSFET to stay off, thereby skipping
pulses. This mode offers the benefits of smaller output
ripple, lower audible noise, and reduced RF interference,
at the expense of lower efficiency when compared to Burst
Mode operation.
Frequency Selection and Clock Synchronization
The switching frequency of the LTC3864 can be selected
using the FREQ pin. If the PLLIN/MODE pin is not being
driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through
an external resistor. Tying FREQ to signal ground selects
350kHz, while floating selects 535kHz. Placing a resistor
between FREQ and signal ground allows the frequency to
be programmed between 50kHz and 850kHz.
The phase-locked loop (PLL) on the LTC3864 will syn-
chronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
the turn-on edge of the external P-channel MOSFET to be
aligned with the rising edge of the synchronizing signal.
The oscillator’s default frequency is based on the operating
frequency set by the FREQ pin. If the oscillator’s default
frequency is near the external clock frequency, only slight
adjustments are needed for the PLL to synchronize the
external P-channel MOSFET’s turn-on edge to the rising
edge of the external clock. This allows the PLL to lock
rapidly without deviating far from the desired frequency.
The PLL is guaranteed from 75kHz to 750kHz. The clock
input levels should be greater than 2V for HI and less
than 0.5V for LO.
Power Good and Fault Protection
The PGOOD pin is an open-drain output. An internal
N-channel MOSFET pulls the PGOOD pin low when the V_FB
pin voltage is outside a ±10% window from the 0.8V internal
voltage reference. The PGOOD pin is also pulled low when
the RUN pin is low (shut down). When the V_FB pin voltage
is within the ±10% window, the MOSFET is turned off and
the pin is allowed to be pulled up by an external resistor
to a source no greater than 6V. The PGOOD open-drain
output has a 100µs delay before it can transition states.
When the V_FB voltage is above +10% of the regulated
voltage of 0.8V, this is considered as an overvoltage con-
dition and the external P-MOSFET is immediately turned
off and prevented from ever turning on until V_FB returns
below +7.5%.
In the event of an output short circuit or overcurrent con-
dition that causes the output voltage to drop significantly
while in current limit, the LTC3864 operating frequency
will fold back. Anytime the output feedback V_FB voltage is
less than 50% of the 0.8V internal reference (i.e., 0.4V),
frequency foldback is active. The frequency will continue
to drop as V_FB drops until reaching a minimum foldback
frequency of about 18% of the setpoint frequency. Fre-
quency foldback is designed, in combination with peak
current limit, to limit current in start-up and short-circuit
conditions. Setting the foldback frequency as a percentage
of operating frequency assures that start-up characteristics
scale appropriately with operating frequency.
3864f
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