LTC3864 Datasheet, PDF (10/28 Pages) Linear Technology – 60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability

LTC3864
OPERATION
Main Control Loop (Refer to Functional Diagram)
The LTC3864 uses a peak current-mode control architec-
ture to regulate the output in an asynchronous step-down
DC/DC switching regulator. The V_FB input is compared to
an internal reference by a transconductance error ampli-
fier (EA). The internal reference can be either a fixed 0.8V
reference V_REF or the voltage input on the SS pin. In normal
operation V_FB regulates to the internal 0.8V reference
voltage. In soft-start or tracking mode, when the SS pin
voltage is less than the internal 0.8V reference voltage,
V_FB will regulate to the SS pin voltage. The error amplifier
output connects to the ITH (current [I] threshold [TH])
pin. The voltage level on the ITH pin is then summed with
a slope compensation ramp to create the peak inductor
current set point.
The peak inductor current is measured through a sense
resistor R_SENSE placed across the V_IN and SENSE pins.
The resultant differential voltage from V_IN to SENSE is
proportional to the inductor current and is compared to the
peak inductor current set point. During normal operation
the P-channel power MOSFET is turned on when the clock
leading edge sets the SR latch through the S input. The
P-channel MOSFET is turned off through the SR latch R
input when the differential voltage from V_IN to SENSE is
greater than the peak inductor current set point and the
current comparator, ICMP, trips high.
Power CAP and V_IN Undervoltage Lockout (UVLO)
Power for the P-channel MOSFET gate driver is derived
from the CAP pin. The CAP pin is regulated to 8V below
V_IN in order to provide efficient P-channel operation. The
power for the V_CAP supply comes from an internal LDO,
which regulates the V_IN-CAP differential voltage. A mini-
mum capacitance of 0.1µF (low ESR ceramic) is required
between V_IN and CAP to assure stability.
For V_IN ≤ 8V, the LDO will be in dropout and the CAP volt-
age will be at ground, i.e. the V_IN-CAP differential voltage
will equal V_IN. If V_IN-CAP is less than 3.25V (typical), the
LTC3864 enters a UVLO state where the GATE is prevented
from switching and most internal circuitry is shut down.
In order to exit UVLO, the V_IN-CAP voltage would have to
exceed 3.5V (typical).
Shutdown and Soft-Start
When the RUN pin is below 0.7V, the controller and most
internal circuits are disabled. In this micropower shutdown
state, the LTC3864 draws only 7µA. Releasing the RUN
pin allows a small internal pull up current to pull the RUN
pin above 1.26V and enable the controller. The RUN pin
can be pulled up to an external supply of up to 60V or it
can be driven directly by logic levels.
The start-up of the output voltage V_OUT is controlled by
the voltage on the SS pin. When the voltage on the SS
pin is less than the 0.8V internal reference, the V_FB pin is
regulated to the voltage on the SS pin. This allows the SS
pin to be used to program a soft-start by connecting an
external capacitor from the SS pin to signal ground. An
internal 10µA pull-up current charges this capacitor, creat-
ing a voltage ramp on the SS pin. As the SS voltage rises
from 0V to 0.8V, the output voltage V_OUT rises smoothly
from zero to its final value.
Alternatively, the SS pin can be used to cause the start-
up of V_OUT to track that of another supply. Typically, this
requires connecting the SS pin to an external resistor
divider from the other supply to ground. (See Applications
Information section.) Under shutdown or UVLO, the SS
pin is pulled to ground and prevented from ramping up.
If the slew rate of the SS pin is greater than 1.2V/ms, the
output will track an internal soft-start ramp instead of the
SS pin. The internal soft-start will guarantee a smooth
start-up of the output under all conditions, including in the
case of a short-circuit recovery where the output voltage
will recover from near ground.
Light Load Current Operation (Burst Mode Operation
or Pulse-Skipping Mode)
The LTC3864 can be enabled to enter high efficiency Burst
Mode operation or pulse-skipping mode at light loads. To
select pulse-skipping operation, tie the PLLIN/MODE pin
to signal ground. To select Burst Mode operation, float
the PLLIN/MODE pin.
In Burst Mode operation, if the V_FB is higher than the refer-
ence voltage, the error amplifier will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
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