LTC3864 Datasheet, PDF (22/28 Pages) Linear Technology – 60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability

LTC3864
APPLICATIONS INFORMATION
resulting junction temperature for the MOSFET can be
calculated at T_A = 70°C, V_IN(MAX) = 55V and I_OUT(MAX) = 2A:
P_PMOS
=
5V
55V
(2A)²
•
1.5
•
105mΩ
+
(55V)²
•
(2A
/
2)
•
100pF
•


0.9Ω
8V – 3V


+
2Ω
3V
•
350kHz
≈ 57mW + 90mW = 147mW
T_J = 70°C+147mW • 60°C/ W ≈ 80°C
The calculations can be repeated for V_IN(MIN) = 5V:
P_PMOS
=
5V
5V
(2A)²
•
1.5
•
105mΩ
+
(5.2V)²
•
100pF
•


0.9Ω
5.2V – 3V
+
2Ω
3V


•
350kHz
≈ 630mW +1mW ≈ 631mW
T_J = 70°C+ 631mW • 60°C / W ≈ 108°C
Next choose an appropriate Schottky diode that will handle
the power requirements. The Diodes Inc. SBR3U100LP
Schottky diode is selected (V_{F(2A,125°C)} = 0.5V, θ_JA = 61°C/W)
for this application. The power dissipation and junction
temperature at T_A = 70°C can be calculated as:
P_DIODE
=
2A
•
_1–
5V
55V


• 0.5V ≈ 909mW
T_J = 70°C+909mW • 61°C/ W = 125°C
These power dissipation calculations show that careful
attention to heat sinking will be necessary.
For the input capacitance, a combination of ceramic and
electrolytic capacitors are chosen to handle the maximum
RMS current of 1A. C_OUT will be selected based on the
ESR that is required to satisfy the output voltage ripple
requirement. For this design, two 47µF ceramic capacitors
are chosen to offer low ripple in both normal operation
and in Burst Mode operation.
A soft-start time of 8ms can be programmed through a
0.1µF capacitor on the SS pin:
C_SS
=
8ms •10µA
0.8V
=
0.1µF
Loop compensation components on the ITH pin are chosen
based on load step transient behavior (as described under
OPTI-LOOP Compensation) and is optimized for stability. A
pull-up resistor is used on the RUN pin for FMEA compli-
ance (see Failure Modes and Effects Analysis).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3864.
1. Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking pur-
poses. Use wide rails and/or entire planes for V_IN, V_OUT
and GND for good filtering and minimal copper loss. If
a ground layer is used, then it should be immediately
below (and/or above) the routing layer for the power
train components which consist of C_IN, sense resistor,
P-MOSFET, Schottky diode, inductor, and C_OUT. Flood
unused areas of all layers with copper for better heat
sinking.
2. Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a
narrow PCB trace (or single via in a multilayer board).
All power train components should be referenced to
power ground and all small signal components (e.g.,
C_ITH1, R_FREQ, C_SS etc.) should be referenced to signal
ground.
3. Place C_IN, sense resistor, P-MOSFET, inductor, and
primary C_OUT capacitors close together in one compact
area. The junction connecting the drain of P-MOSFET,
cathode of Schottky, and (+) terminal of inductor (this
junction is commonly referred to as switch or phase
node) should be compact but be large enough to handle
3864f
22