LTC3864 Datasheet, PDF (23/28 Pages) Linear Technology – 60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability

LTC3864
APPLICATIONS INFORMATION
the inductor currents without large copper losses. Place
the sense resistor and source of P-channel MOSFET
as close as possible to the (+) plate of C_IN capacitor(s)
that provides the bulk of the AC current (these are
normally the ceramic capacitors), and connect the
anode of the Schottky diode as close as possible to
the (–) terminal of the same C_IN capacitor(s). The high
dI/dt loop formed by C_IN, the MOSFET, and the Schottky
diode should have short leads and PCB trace lengths to
minimize high frequency EMI and voltage stress from
inductive ringing. The (–) terminal of the primary C_OUT
capacitor(s) which filter the bulk of the inductor ripple
current (these are normally the ceramic capacitors)
should also be connected close to the (–) terminal of C_IN.
4. Place pins 7 to 12 facing the power train components.
Keep high dV/dt signals on GATE and switch away from
sensitive small signal traces and components.
5. Place the sense resistor close to the (+) terminal of C_IN
and source of P-MOSFET. Use a Kelvin (4-wire) con-
nection across the sense resistor and route the traces
together as a differential pair into the V_IN and SENSE
pins. An optional RC filter could be placed near the V_IN
and SENSE pins to filter the current sense signal.
6. Place the resistive feedback divider R_FB1/2 as close as
possible to the V_FB pin. The (+) terminal of the feedback
divider should connect to the output regulation point
and the (–) terminal of feedback divider should connect
to signal ground.
7. Place the ceramic C_CAP capacitor as close as possible
to V_IN and CAP pins. This capacitor provides the gate
discharging current for the power P-MOSFET.
8. Place small signal components as close to their respec-
tive pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
V_FB, ITH, and R_FREQ pins. Use sufficient isolation when
routing a clock signal into PLLIN /MODE pin so that the
clock does not couple into sensitive small signal pins.
Failure Mode and Effects Analysis (FMEA)
A FMEA study on the LTC3864 has been conducted through
adjacent pin opens and shorts. The device was tested
in a step-down application (Figure 8) from V_IN = 12V to
V_OUT = 5V with a current load of 1A on the output. One
group of tests involved the application being monitored
while each pin was disconnected from the PC board
and left open while all other pins remained intact. The
other group of tests involved each pin being shorted to
its adjacent pins while all other pins were connected as
it would be normally in the application. The results are
shown in Table 2.
For FMEA compliance, the following design implementa-
tions are recommended:
• If the RUN pin is being pull-up to a voltage greater than
6V, then it is done so through a pull-up resistor (100k
to 1M) so that the PGOOD pin is not damaged in case
of a RUN to PGOOD short.
• The gate of the external P-MOSFET be pulled through
a resistor (20k to 100k) to the input supply, V_IN so that
the P-MOSFET is guaranteed to turn off in case of a
GATE open.
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