LTC3864 Datasheet, PDF (14/28 Pages) Linear Technology – 60V Low IQ Step-Down DC/DC Controller with 100% Duty Cycle Capability

LTC3864
APPLICATIONS INFORMATION
The peak inductor current limit is equal to:
I_{L(PEAK )}
≅


95mV
R_SENSE


This inductor current limit would translate to an output
current limit based on the inductor ripple:
I_LIMIT
≅
95mV
R_SENSE
–
∆I_L
2
The SENSE pin is a high impedance input with a maximum
leakage of ±2µA. Since the LTC3864 is a peak current
mode controller, noise on the SENSE pin can create pulse
width jitter. Careful attention must be paid to the layout of
R_SENSE. To ensure the integrity of the current sense signal,
V_SENSE, the traces from V_IN and SENSE pins should be
short and run together as a differential pair and Kelvin
(4-wire) connected across R_SENSE (Figure 3).
V_IN
LTC3864
SENSE
OPTIONAL
FILTERING
C_F
R_F
V_IN
R_SENSE
MP
3864 F03
Figure 3. Inductor Current Sensing
The LTC3864 has internal filtering of the current sense
voltage which should be adequate in most applications.
However, adding a provision for an external filter offers
added flexibility and noise immunity, should it be neces-
sary. The filter can be created by placing a resistor from the
R_SENSE resistor to the SENSE pin and a capacitor across
the V_IN and SENSE pins.
Power MOSFET Selection
The LTC3864 drives a P-channel power MOSFET that
serves as the main switch for the asynchronous step-
down converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown voltage
V_BR(DSS), threshold voltage V_GS(TH), on-resistance R_DS(ON),
gate-to-drain reverse transfer capacitance C_RSS, maximum
14
drain current I_D(MAX), and the MOSFET’s thermal resistance
θ_JC(MOSFET) and θ_JA(MOSFET).
The gate driver bias voltage V_IN-V_CAP is set by an internal
LDO regulator. In normal operation, the CAP pin will be
regulated to 8V below V_IN. A minimum 0.1µF capacitor
is required across the V_IN and CAP pins to ensure LDO
stability. If required, additional capacitance can be added
to accommodate higher gate currents without voltage
droop. In shutdown and Burst Mode operation, the CAP
LDO is turned off. In the event of CAP leakage to ground,
the CAP voltage is limited to 9V by a weak internal clamp
from V_IN to CAP. As a result, a minimum 10V V_GS rated
MOSFET is required.
The power dissipated by the P-channel MOSFET when the
LTC3864 is in continuous conduction mode is given by:
P_MOSFET ≅ D • I_OUT2 • ρ_τ • R_DS(ON) +
V_IN2
•


I_O2UT
•
(C_MILLER)
•
( ) ^


V_IN
–
R_DN
V_CAP –
V_MILLER
+
R_UP
V_MILLER



•
f
where D is duty factor, R_DS(ON) is on-resistance of
P-MOSFET, ρ_t is temperature coefficient of on-resistance,
R_DN is the pull-down driver resistance specified at 0.9Ω
typical and R_UP is the pull-up driver resistance specified at
2Ω typical. V_MILLER is the Miller effective V_GS voltage and
is taken graphically from the power MOSFET data sheet.
The power MOSFET input capacitance C_MILLER is
the most important selection criteria for determin-
ing the transition loss term in the P-channel MOSFET
but is not directly specified on MOSFET data sheets.
C_MILLER is a combination of several components, but
it can be derived from the typical gate charge curve
included on most data sheets (Figure 4). The curve is
MILLER EFFECT
V_SG
a
b
G
I_GATE
S
D
R_LOAD
+
– ^VSD(TEST)
Q_IN
C_MILLER = (Q_B – Q_A)/V_SD(TEST)
(a)
3864 F04
(b)
Figure 4. (a) Typical P-MOSFET Gate Charge Characteristics
and (b) Test Set-Up to Generate Gate Charge Curve
3864f