LTC3728LCGN-PBF Datasheet, PDF(24/38 Page) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Regulators

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LTC3728LCGN-PBF Datasheet, PDF (24/38 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Regulators

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LTC3728L/LTC3728LX

Applications Information

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin.

If the external frequency (fPLLIN) is greater than the os-

cillator frequency, f0SC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency is

less than f0SC, current is sunk continuously, pulling down

the PLLFLTR pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. Thus, the voltage on the PLLFLTR pin

is adjusted until the phase and frequency of the external

and internal oscillators are identical. At this stable operat-

ing point, the phase comparator output is open and the

filter capacitor CLP holds the voltage. The ICâs PLLIN pin

must be driven from a low impedance source such as a

logic gate located close to the pin. When using multiple

ICs for a phase-locked system, the PLLFLTR pin of the

master oscillator should be biased at a voltage that will

guarantee the slave oscillator(s) ability to lock onto the

masterâs frequency. A DC voltage of 0.7V to 1.7V applied

to the master oscillatorâs PLLFLTR pin is recommended

in order to meet this requirement. The resultant operating

frequency can range from 300kHz to 500kHz.

The loop filter components (CLP, RLP) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components, CLP and RLP , determine how fast the loop

acquires lock. Typically, RLP = 10kÎ© and CLP is 0.01ÂµF

to 0.1ÂµF.

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time dura-

tion that each controller is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

tON(MIN)

VOUT

VIN(f)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The typical tested minimum on-time is 100ns under an ideal

condition without switching noise. However, the minimum

on-time can be affected by PCB switching noise in the

voltage and current loops. With a reasonably good PCB

layout, a minimum 30% inductor current ripple, approxi-

mately 15mV sensing ripple voltage and 200ns minimum

on-time are conservative estimates for starting a design.

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding

or as a logic-level input. Continuous operation is forced

on both controllers when the FCB pin drops below 0.8V.

During continuous mode, current flows continuously in

the transformer primary. The secondary winding(s) draw

current only when the bottom, synchronous switch is on.

When primary load currents are low and/or the VIN/VOUT

ratio is low, the synchronous switch may not be on for a

sufficient amount of time to transfer power from the output

capacitor to the secondary load. Forced continuous opera-

tion will support secondary windings providing there is

sufficient synchronous switch duty factor. Thus, the FCB

input pin removes the requirement that power must be

drawn from the inductor primary in order to extract power

from the auxiliary windings. With the loop in continuous

mode, the auxiliary outputs may nominally be loaded

without regard to the primary output load.

The secondary output voltage, VSEC, is normally set as

shown in Figure 6a by the turns ratio N of the transformer:

VSEC @ (N + 1) VOUT

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current,

then VSEC will droop. An external resistive divider from

VSEC to the FCB pin sets a minimum voltage VSEC(MIN):

VSEC(MIN)

0.8V

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where R5 and R6 are shown in Figure 2.

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