LTC3728LCGN-PBF Datasheet, PDF (23/38 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Regulators

LTC3728L/LTC3728LX
applications information
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
The value of the soft-start capacitor C_SS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C_SS > (C_OUT )(V_OUT) (10 ^–4) (R_SENSE)
The minimum recommended soft-start capacitor of C_SS =
0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The current comparators have a maximum sense volt-
age of 75mV resulting in a maximum MOSFET current
of 75mV/R_SENSE. The maximum value of current limit
generally occurs with the largest V_IN at the highest ambi-
ent temperature, conditions that cause the highest power
dissipation in the top MOSFET.
Each controller includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch previously described is overridden. If the
output falls below 70% of its nominal output level, then
the maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the controller will begin cycle skipping
in order to limit the short-circuit current. In this situation,
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t_ON(MIN)
of each controller (typically 100ns), the input voltage and
inductor value:
∆I_L(SC) = t_ON(MIN) (V_IN/L)
The resulting short-circuit current is:
I_SC
=
25mV
R_SENSE
–
1
2
∆I_L(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the controller
is operating.
A comparator monitors the output for overvoltage con-
ditions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage. When
this condition is sensed, the top MOSFET is turned off
and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator
is only latched by the overvoltage condition itself and
will, therefore, allow a switching regulator system hav-
ing a poor PC layout to function while the design is being
debugged. The bottom MOSFET remains on continuously
for as long as the OV condition persists. If V_OUT returns
to a safe level, normal operation automatically resumes. A
shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This al-
lows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage controlled oscillator is ± 50% around the center
frequency f_O. A voltage applied to the PLLFLTR pin of 1.2V
corresponds to a frequency of approximately 400kHz. The
nominal operating frequency range of the IC is 260kHz to
550kHz.
The phase detector used is an edge-sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal oscillators. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, ∆f_H,
is equal to the capture range, ∆f_C:
∆f_H = ∆f_C = ±0.5 f_O (260kHz-550kHz)
3728lxff
23