LTC3728LCGN-PBF Datasheet, PDF (10/38 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Regulators

LTC3728L/LTC3728LX
Pin Functions
V_OSENSE1, V_OSENSE2: Error Amplifier Feedback Input.
Receives the remotely sensed feedback voltage for each
controller from an external resistive divider across the
output.
PLLFLTR: Filter Connection for Phase-Locked Loop. Alter-
natively, this pin can be driven with an AC or DC voltage
source to vary the frequency of the internal oscillator.
PLLIN: External Synchronization Input to Phase Detector.
This pin is internally terminated to SGND with 50kΩ. The
phase-locked loop will force the rising top gate signal of
controller 1 to be synchronized with the rising edge of
the PLLIN signal.
FCB: Forced Continuous Control Input. This input acts
on both controllers and is normally used to regulate a
secondary winding. Pulling this pin below 0.8V will force
continuous synchronous operation.
I_TH1, I_TH2: Error Amplifier Output and Switching Regulator
Compensation Point. Each associated channels’ current
comparator trip point increases with this control voltage.
SGND: Small Signal Ground. Common to both con-
trollers, this pin must be routed separately from high
current grounds to the common (–) terminals of the C_OUT
capacitors.
3.3V_OUT: Linear Regulator Output. Capable of supplying
10mA DC with peak currents as high as 50mA.
NC: No Connect.
SENSE2^–, SENSE1^–: The (–) Input to the Differential Cur-
rent Comparators.
SENSE2⁺, SENSE1⁺: The (+) Input to the Differential Current
Comparators. The I_TH pin voltage and controlled offsets
between the SENSE^– and SENSE⁺ pins in conjunction with
R_SENSE set the current trip threshold.
RUN/SS2, RUN/SS1: Combination of soft-start, run control
inputs and short-circuit detection timers. A capacitor to
ground at each of these pins sets the ramp time to full
output current. Forcing either of these pins back below
1.0V causes the IC to shut down the circuitry required for
that particular controller. Latchoff overcurrent protection is
also invoked via this pin as described in the Applications
Information section.
10
TG2, TG1: High Current Gate Drives for Top N-Channel
MOSFETs. These are the outputs of floating drivers with
a voltage swing equal to INTV_CC – 0.5V superimposed on
the switch node voltage SW.
SW2, SW1: Switch Node Connections to Inductors. Voltage
swing at these pins is from a Schottky diode (external)
voltage drop below ground to V_IN.
BOOST2, BOOST1: Bootstrapped Supplies to the Top-
side Floating Drivers. Capacitors are connected between
the boost and switch pins and Schottky diodes are tied
between the boost and INTV_CC pins. Voltage swing at the
boost pins is from INTV_CC to (V_IN + INTV_CC).
BG2, BG1: High Current Gate Drives for Bottom (Synchro-
nous) N-Channel MOSFETs. Voltage swing at these pins
is from ground to INTV_CC.
PGND: Driver Power Ground. Connects to the sources
of bottom (synchronous) N-channel MOSFETs, anodes
of the Schottky rectifiers and the (–) terminal(s) of C_IN.
INTV_CC: Output of the Internal 5V Linear Low Dropout
Regulator and the EXTV_CC Switch. The driver and control
circuits are powered from this voltage source. Must be
decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor.
EXTV_CC: External Power Input to an Internal Switch
Connected to INTV_CC. This switch closes and supplies
V_CC power, bypassing the internal low dropout regulator,
whenever EXTV_CC is higher than 4.7V. See EXTV_CC connec-
tion in Applications section. Do not exceed 7V on this pin.
V_IN: Main Supply Pin. A bypass capacitor should be tied
between this pin and the signal ground pin.
PGOOD: Open-Drain Logic Output. PGOOD is pulled to
ground when the voltage on either V_OSENSE pin is not
within ±7.5% of its set point.
Exposed Pad (UH Package Only): Signal Ground. Must
be soldered to the PCB, providing a local ground for the
control components of the IC, and be tied to the PGND
pin under the IC.
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