LTC3786_15 Datasheet, PDF (22/34 Pages) Linear Technology – Low IQ Synchronous Boost Controller

LTC3786
Applications Information
The R_SENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R_SENSE
≤
75mV
9.25A
=
0.008Ω
Choosing 1% resistors: R_A = 5k and R_B = 95.3k yields an
output voltage of 24.072V.
The power dissipation on the topside MOSFET in each chan-
nel can be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: R_DS(ON) = 0.012Ω, C_MILLER = 150pF. At
maximum input voltage with T(estimated) = 50°C:
P_MAIN
=
(^{24V – 12V})^24V
(^12V)²
•
(^4A)²
•^1+ ₍0.005_{) (}50°C – 25°C₎^ • 0.008Ω
+ ₍1.7₎₍24V₎^{3 4A} ₍150pF₎₍350kHz₎ = 0.7W
12V
C_OUT is chosen to filter the square current in the output.
The maximum output current peak is:
I_{OUT(PEAK )}
=
I_{OUT(MAX )}
•
₁₊
RIPPLE%
2


=
4
•
₁₊
31%
2


=
4.62A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 23.1mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 6. Figure 7 illustrates the current
waveforms present in the various branches the synchro-
nous regulator operating in the continuous mode. Check
the following in your layout:
1. Put the bottom N-channel MOSFET MBOT and the top
N-channel MOSFET MTOP in one compact area with
C_OUT .
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C_INTVCC must return to the combined C_OUT (–)
terminals. The path formed by the bottom N-channel
MOSFET and the capacitor should have short leads and
PC trace lengths. The output capacitor (–) terminals
should be connected as close as possible to the (–)
source terminal of the bottom MOSFET.
3. Does the LTC3786 VFB pin’s resistive divider connect
to the (+) terminal of C_OUT? The resistive divider must
be connected between the (+) terminal of C_OUT and
signal ground and placed close to the VFB pin. The
feedback resistor connections should not be along the
high current input feeds from the input capacitor(s).
4. Are the SENSE^– and SENSE⁺ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE⁺ and SENSE^– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
5. Is the INTV_CC decoupling capacitor connected close
to the IC, between the INTV_CC and the power ground
pin? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTV_CC and GND pins can help
improve noise performance substantially.
6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes. All of these nodes have very large and fast
moving signals and, therefore, should be kept on the
output side of the LTC3786 and occupy a minimal PC
trace area.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV_CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the GND pin of the IC.
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