LTC3786_15 Datasheet, PDF (19/34 Pages) Linear Technology – Low IQ Synchronous Boost Controller

LTC3786
Applications Information
A leaky diode D_B in the boost converter can not only
prevent the top MOSFET from fully turning on but it can
also completely discharge the bootstrap capacitor C_B and
create a current path from the input voltage to the BOOST
pin to INTV_CC. This can cause INTV_CC to rise if the diode
leakage exceeds the current consumption on INTV_CC.
This is particularly a concern in Burst Mode operation
where the load on INTV_CC can be very small. The external
Schottky or silicon diode should be carefully chosen such
that INTV_CC never gets charged up much higher than its
normal regulation voltage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on-chip
(such as an INTV_CC short to ground), the overtemperature
shutdown circuitry will shut down the LTC3786. When the
junction temperature exceeds approximately 170°C, the
overtemperature circuitry disables the INTV_CC LDO, causing
the INTV_CC supply to collapse and effectively shut down
the entire LTC3786 chip. Once the junction temperature
drops back to approximately 155°C, the INTV_CC LDO turns
back on. Long-term overstress (T_J > 125°C) should be
avoided as it can degrade the performance or shorten
the life of the part.
Since the shutdown may occur at full load, beware that
the load current won’t result in high power dissipation in
the body diodes of the top MOSFET. In this case, PGOOD
output may be used to turn the system load off.
Phase-Locked Loop and Frequency Synchronization
The LTC3786 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the bottom MOSFET to be locked to the rising
edge of an external clock signal applied to the PLLIN/MODE
pin. The phase detector is an edge-sensitive digital type
that provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced continu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than f_OSC,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
C_LP , holds the voltage at the VCO input.
Typically, the external clock (on PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.2V.
Note that the LTC3786 can only be synchronized to an
external clock whose frequency is within range of the
LTC3786’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
1000
900
800
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3786 F05
Figure 5. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
3786fa
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