LTC3786_15 Datasheet, PDF (21/34 Pages) Linear Technology – Low IQ Synchronous Boost Controller

LTC3786
Applications Information
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, V_OUT shifts by an amount equal
to ∆I_LOAD(ESR), where ESR is the effective series resistance
of C_OUT . ∆I_LOAD also begins to charge or discharge C_OUT
generating the feedback error signal that forces the regula-
tor to adapt to the current change and return V_OUT to its
steady-state value. During this recovery time V_OUT can
be monitored for excessive overshoot or ringing, which
would indicate a stability problem. OPTI‑LOOP^® compen-
sation allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
availability of the ITH pin not only allows optimization of
control loop behavior, but it also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown
in the Figure 8 circuit will provide an adequate starting
point for most applications.
The ITH series R_C-C_C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PCB layout
is complete and the particular output capacitor type and
value have been determined. The output capacitors must
be selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1µs to
10µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET and load resistor directly
across the output capacitor and driving the gate with an
appropriate pulse generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current
may not be within the bandwidth of the feedback loop,
so this signal cannot be used to determine phase margin.
This is why it is better to look at the ITH pin signal which
is in the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing
R_C and the bandwidth of the loop will be increased by
decreasing C_C. If R_C is increased by the same factor that
C_C is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT , causing a rapid drop in V_OUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C_LOAD to C_OUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • C_LOAD. Thus, a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example, assume V_IN = 12V(nominal),
V_IN = 22V (max), V_OUT = 24V, I_OUT(MAX) = 4A, V_SENSE(MAX)
= 75mV and f = 350kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. Tie the MODE/PLLIN pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:
∆I_L
=
V_IN

1–
f •L_
V_IN
V_OUT



The largest ripple happens when V_IN = 1/2V_OUT = 12V,
where the average maximum inductor is I_MAX = I_OUT(MAX)
• (V_OUT/V_IN) = 8A. A 6.8µH inductor will produce a 31%
ripple current. The peak inductor current will be the maxi-
mum DC value plus one-half the ripple current, or 9.25A.
3786fa
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