XPIO110GXS Datasheet, PDF (7/23 Pages) Lattice Semiconductor – Fully Integrated 10Gbps Serializer/Deserializer Device

Lattice Semiconductor
XPIO 110GXS Data Sheet
Mode 2: Synchronous line loopback with clock clean-up. Driving LB_P622_Enb low enables line loopback
mode. In order to make this loopback mode SONET/SDH compliant the CK622OUT_P/N must be connected to a
VCXO-powered PLL chip (e.g. MAX3670), and CK622OUT_SEL pulled/driven high. The output of the PLL provides
a low jitter reference clock that is in phase with the data presented at the LVDS parallel outputs. This reference
clock is connected to REF_CK_P/N. As in Mode 1 a separate reference clock is input to RX_REF_CK_P/N to drive
the CDR logic. Data on the TX_D_P/N and RX_D_P/N pins are now synchronous, and the data repeated on
TX_D_P/N meets SONET/SDH line loopback application requirements.
Figure 4. Line Loopback Mode 2 Block Diagram
LB_LVDS_ENb=1
LVDS Loopback
Mode 1
BIST_ENb=0
BIST_LB_SC0=0
BIST_LB_SC1=1
RX_D_LV[0..15]
RX
1
LVDS
0
RX_CK_LV_P/N
Data
Deserializer
10G RX
RX_D_P
RX_D_N
LB_P622_ENb=0
Parallel
Loopback
TX_D_LV[0..15]
TX_CL_LV_P/N
REF_CK_P/N
CK622_OUT_PN
CK622OUT_SEL = 1
TX
LVDS
Data
1
Serializer
0
CMU
External Low Jitter PLL
(e.g. MAX 3670)
Low Jitter Clock
Synchronous to
REF_CK_P/N
To REF_CK_P/N
10G TX
TX_D_P
TX_D_N
Reference
PLL
Reference Clocks
There are two AC coupled reference clock input pairs, REF_CK_P/N, and RX_REF_CK_P/N. The CDR block is
driven by either REF_CK_P/N or RX_REF_CK_P/N. The CMU block is only driven by REF_CK_P/N. The reference
clock input frequency for REF_CK_P/N can be either 1/16^th (622MHz) or 1/64^th (155MHz) the transmitter/receiver
data rate. Likewise, RX_REF_CK_P/N can be 1/16^th or 1/64^th the 10Gbps receiver rate. RX_REF_CK_P/N and
REF_CK_P/N are configured in tandem to 1/16^th or 1/64^th by REF_CK_SEL. They cannot be configured indepen-
dently. AC coupling for all reference clocks is recommended.
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