XPIO110GXS Datasheet, PDF (5/23 Pages) Lattice Semiconductor – Fully Integrated 10Gbps Serializer/Deserializer Device

Lattice Semiconductor
XPIO 110GXS Data Sheet
The external reference clock is essential for the CDR block. The reference clock provides two functions: One func-
tion is training the VCO in the CDR PLL to the serial data-stream frequency. The other is to generate a stable clock
when the input serial data is absent. The CDR PLL creates an internal reference frequency. The reference fre-
quency is monitored, and a loss of lock is asserted when it goes out of specification.
Lock Detect
The XPIO 110GXS implements a CDR lock detector circuit that monitors the frequency of the internal clock.
RX_LOCK is asserted whenever a REF_CK or RX_REF_CK are operating within specification. RX_LOCK is deas-
serted under some specific circumstances:
1. When RX_RESETb is asserted (i.e. ‘0’)
2. When the REF_CK (or RX_REF_CK) is not present.
3. When the clock recovered from the incoming datastream falls outside the range specified by the
SC_LOCK_DIFF input pins. When the recovered clock is out of range, RX_LOCK will deassert briefly and then
be reasserted as it relocks to the REF_CK (RX_REF_CK). This effectively leaves the RX_LOCK signal toggling
as it attempts to reacquire the clock embedded in the RX_D_P/N data inputs.
Deserialization
The XPIO 110GXS uses a 1:16 demultiplexer to deserialize the high speed data from the CDR. The demultiplexer
generates the 16 bit parallel data stream. The bit order presented on the RX_D_LV_P/N[0..15] LVDS outputs mir-
rors the order on the TX_D_LV[0..15]P/N LVDS inputs. The first data bit received by the CDR is present on
RX_D_LV_P/N[15] when SC_LSB1STb is connected to a logic high, and it is present on RX_D_LV_P/N[0] when
SC_LSB1STb is connected to a logic low.
LVDS Data Transmitter
The 16-bit parallel data and clock are sent out via the RX_D_LV_P/N[0..15] and RX_LV_CK_P/N LVDS pins,
respectively. Data on the RX_D_LV_P/N pins is synchronous to the RX_LV_CK_P/N output pins. The data coming
in on the RX_D_P/N pins requires around five clocks to arrive at the RX_D_LV_P/N outputs. The output current of
the LVDS outputs is adjustable using the SC_LV_ISET[1:0] configuration pins. System designers can use these
pins to optimize the LVDS receive data performance.
XFP Module Considerations
The XPIO110GXS was conceived and implemented prior to the finalization of the XFP specification. The implica-
tion of this is the CML TX voltage swing is typically higher than that specified in the XFP MSA documents.
The XFP MSA specification indicates a XFP module should accept a maximum of 800mV input swing. In practice it
is the individual XFP module internal architecture that defines the maximum range. However, most XFP modules
simply rate themselves to the 800mV specification regardless of the likelihood they may operate beyond the range
specified in the XFP MSA.
Actual operation of the XPIO110GXS with existing XFP modules shows these still operate with the CML swing set
to the default TX_CML_ISET[1:0] = “11”. In order to more closely match the XFP specification a
TX_CML_ISET[1:0] = “01” configuration is recommended. This places the typical output swing from the CML TX
outputs at 650mV to 1100mV.
Loopback Operation
The XPIO 110GXS supports several loopback operations to provide diagnostic functions and to aid in performing
SONET/SDH functional tests.
LVDS Diagnostic Loopback
In LVDS loopback mode, 16 bit-wide data is fed into the TX LVDS input. The XPIO 110GXS routes data from the
LVDS transmit interface to the internal receiver interface, and then repeats the data at the LVDS RX output.
To enable this mode of operation set BIST_ENb=0, LB_LVDS_ENb=0, and BIST_LB_SC[1:0]=10.
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