XPIO110GXS Datasheet, PDF (22/23 Pages) Lattice Semiconductor – Fully Integrated 10Gbps Serializer/Deserializer Device

Lattice Semiconductor
XPIO 110GXS Data Sheet
Input and Analog Pin Assignments and Descriptions¹ (Continued)
Pin Name
Pin Description
TX_CK_LV_PA[0]
TX_CK_LV_PA[1]
LVDS TX clock adjustment for 622 MHz or 311 MHz mode.
TX_D_EN
10 Gbps CML TX enable.
TX_CK622_PA[1]
TX_CK622_PA[0]
CLK622 timing adjustment.
PWDN_TXb
TX power down.
PWDN_RXb
RX power down.
RESET_RXb
RX reset.
CK622OUT_SEL
CK622 enable.
REF_CK_SEL
Ref CLK frequency selection.
RX_LV_EN
LVDS output enable.
TX_CP_ISET[1]
TX_CP_ISET[0]
TX charge pump current setting.
TX_LV_PLLBPb
LVDS PLL bypass. Inverting phase of 622M clock
TX_CK_LV_P/N is used to sample the input parallel data.
TX_CK_LV_SEL
Sets TX_CK_LV_P/N frequency.
BIST ENb
Enable built-in self test. Used for LVDS loopback.
BIST LB SC[1]
TX_CP_ISE[0]
Configures LVDS loopback
1. All LVCMOS/In pins have built-in pullup resistors.
2. REF_CK is the CDR reference clock when RX_REF_CK_Enb = 1.
Function
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
Flip-chip
BGA
Ball #
G7
C3
J6
P2
N6
P5
N16
R6
P6
P8
R9
R3, M5
E9
G9
E5
D2, E3
22