XPIO110GXS Datasheet, PDF (4/23 Pages) Lattice Semiconductor – Fully Integrated 10Gbps Serializer/Deserializer Device

Lattice Semiconductor
XPIO 110GXS Data Sheet
The FIFO circuitry indicates an overflow or underflow condition by asserting TX_FIFO_ERR high. The
TX_FIFO_ERR only provides status information about an overflow or underflow. It does not indicate which of the
two events actually occurred. During the period of time when the TX_FIFO_ERR signal is asserted, the TX_D_P/N
pins toggle at a constant rate. This prevents the AC coupling capacitors from becoming blocking capacitors.
The transmit FIFO’s read and write pointers can be recentered by asserting the TX_FIFO_INIT pin high. Thus, one
way to automatically recenter the FIFO read/write pointers after TX_FIFO_ERR is asserted is to connect
TX_FIFO_INIT and TX_FIFO_ERR together.
The FIFO read/write pointers are re-centered after:
• Device power on reset
• Transmitter reset (asserting RESET_TXb low)
• CMU PLL is out of lock
Serialization
The output data bus from the FIFO feeds a 16:1 serializer to generate a 9.953 Gbps (OC-192 rate) data stream.
The high-speed clock (TX_CLK) is a low jitter clock generated by the CMU. The serializer uses TX_CLK to clock
out high-speed data.
TX CML Driver
The serial data stream in turn becomes an input to a differential high-speed CML data driver. The TX_D CML driver
incorporates an internal 50-ohm termination resistor on both P and N branches for impedance matching with the
PCB transmission line. The CML output may require AC coupling (as in Figure 5). The output current of the CML
driver can be adjusted using two configuration pins, TX_CML_ISET[1:0]. These configuration pins are used to bal-
ance power consumption and performance.
In normal operation, the data presented at the LVDS TX inputs requires about nine clocks to transit the various
logic blocks before being presented at the TX CML driver output.
Clock-Multiplier-Unit (CMU)
The CMU consists of a differential PLL that is capable of producing a very low jitter serial clock. The clock is gener-
ated through a reference clock (REF_CLK_P/N) at either 1/16^th or 1/64^th the data transmission rate (This is nomi-
nally 622.08 or 155.52 MHz for OC-192 data rates). This reference clock must be generated from a differential
crystal oscillator that has a frequency accuracy of better than ±20ppm for SONET applications.
The CMU PLL can provide a phase-adjustable parallel data rate clock (CK622OUT_P/N) that is 1/16^th the transmit
data rate to clock other devices or systems. The output of CK622OUT_P/N meets the LVDS signaling specifica-
tions. Using the TX_CK622_PA[1:0] configuration pins, the phase can be adjusted in T/4 increments, where T is the
period of the clock for the parallel interface.
Receiver
Limiting Amplifier
The XPIO 110GXS 10 Gbps CMOS receiver integrates a highly sensitive limiting amplifier. The XPIO 110GXS also
implements an amplifier offset compensation technology that works in conjunction with the limiting amplifier to
achieve superior amplifier input sensitivity. Sufficient gain is designed into the limiting amplifier to detect a peak-to-
peak differential input as small as 50mV. This attenuated signal can be properly detected and amplified to satura-
tion.
Clock and Data Recovery (CDR)
One of the most critical circuits in the receiver is the clock and data recovery (CDR) block. The CDR block extracts
the clock from an incoming high-speed, non-return to zero (NRZ) data, and retimes the data based on an external
reference clock. Extraction of the clock embedded in the serial data-stream is performed through comparison of the
phase relationship between transitions of the data and the external reference clock.
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