XPIO110GXS Datasheet, PDF (19/23 Pages) Lattice Semiconductor – Fully Integrated 10Gbps Serializer/Deserializer Device

Lattice Semiconductor
XPIO 110GXS Data Sheet
Common Pin Assignments and Descriptions⁴
Pad Name
Pin Description
Flip-chip BGA Ball Number⁴
RX analog circuit ground
E16, K14, L14, M15
TX analog circuit ground
F3, L5
GND^{1, 3}
I/O ground
Logic circuit ground
D8, D9, E8, F7, F8, G8, H7, H8, H9, H10, J8, J9, J10, K8, K9, K10, L9,
L10, M10, N10, P10, R10, R11, R12
C1, D12, D13, J12, M12, M16, N7, N14, P14, P15, R1
PLL ground
C12
High-speed limit amplifier ground
F14, G13, H13, J14
High-speed transmitter driver ground F4, G5, H5, J4, K4, L4
VDDAR
RX analog circuit power
E11, F10, J15, J16
VDDAT
TX analog circuit power
M1, R8
VDDH
I/O power
C4, C5, C6, C7, C8, C9, C10, C11, D5, D10, D11, K11, L7, L8, L11, M6,
M7, M8, M9, M11, N11, N12, P9, P11, P12
VDDL
Logic circuit power
D4, E6, L12, R15, E10
VDDR
High-speed limit amplifier power
F15, F16
VDDT
High-speed transmitter driver power J2, J3, M3
VDDAR25 Reference circuit power
J11
VDDAT25 Reference circuit power
F1
NC²
No connect
C2, C14, C15, C16, C17, D1, D14, D16, E1, E2, E4, E7, E13, E14, F5,
F6, F12, F13, F17, G4, G6, G10, G11, H4, H6, H12, J7, J13, J17, K5,
K6, K7, K12, K13, L6, L13, M2, M13, N2, N3, N5, N8, N9, N17, P3, P4,
P7, P16, P17, R2, R14
1. All grounds must be electrically connected at the board level.
2. NC pins should not be connected to any active signals, V_DD or GND.
3. Balls for GND, VDDAR, VDDAT, VDDH, VDDL, VDDR, VDDT, VDDAR25 and VDDAT25 are connected within the substrate to their respec-
tive common signals.
4. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
ascending horizontally.
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