XPIO110GXS Datasheet, PDF (14/23 Pages) Lattice Semiconductor – Fully Integrated 10Gbps Serializer/Deserializer Device

Lattice Semiconductor
XPIO 110GXS Data Sheet
Configuration Pin Descriptions (Continued)
Pin Name
State
Action
RX_LOS_POL = 0
RX_LOS_POL = 1
RX_LOS
1
Asserted by the receiver to indi-
cate it has lost the data signal.
Receiver OK
0
Receiver OK
Asserted by the receiver to indicate it
has lost the data signal.
RX_LOS_POL
1
RX_LOS is an active-low input
0
RX_LOS is an active-high input.
RX_D_RP_ENb
1
RX_D_RP_P/N signals are inactive
0
RX_D_RP_P/N signals are active
RX_LOCK2REFb³
1
RX_PLL locks to the recovered receive data clock.
0
RX_PLL locks to the REF_CK or RX_REF_CK input
11
SC_LOCK_DIFF[1:0]³
10
01
See LOCK_TOL in the High Speed Input/Output Specifications section of
this data sheet.
00
11
SC_LV_ISET[1:0]
10
See V_OS in the Low Speed Input/Output Specifications section of this data
01
sheet.
00
RX_LV_EN
1
RX_D_LV_P/N[15:0] are enabled
0
RX_D_LV_P/N[15:0] are disabled
PWDN_RXb
1
Receiver is operating
0
Receiver is powered down
RESET_RXb
1
Receiver normal operation
0
Resets the receiver logic.
General Controls
CK622OUT_SEL
1
CK622 sourced by CDR
0
CK622 sourced by CMU
SC_LSB1STb
TX_D_LV_P/N[15] transmitted over TX_D_P/N first
1
RX_D_LV_P/N[15] first bit received from RX_D_P/N (e.g. SONET appli-
cations)
TX_D_LV_P/N[0] transmitted over TX_D_P/N first
0
RX_D_LV_P/N[0] first bit received from RX_D_P/N (e.g. 10GE applica-
tions)
REF_CK_SEL⁴
1
REF_CK is 1/16 of frequency (622.08MHz for OC-192)
0
REF_CK is 1/64 of frequency (155.52MHz for OC-192)
BIST_ENb
1
Normal operation, built-in self tests are disabled.
0
Built-in self test enabled. Enable this for LVDS loopback mode only.
11
Invalid
BIST_LB_SC[1:0]
10
LVDS loopback mode enable
01
Invalid
00
Invalid
1. Only available when CK622OUT_SEL = 0 (CMU CLK Mode).
2. T = period
3. Locks to REF_CK when RX_REF_CK_Enb = 1. Locks to RX_REF_CK when RX_REF_CK_Enb = 0.
4. Applies to RX_REF_CK also.
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