XPIO110GXS Datasheet, PDF (21/23 Pages) Lattice Semiconductor – Fully Integrated 10Gbps Serializer/Deserializer Device

Lattice Semiconductor
XPIO 110GXS Data Sheet
Input and Analog Pin Assignments and Descriptions¹
Pin Name
Pin Description
RX_D_P, RX_D_N
10 Gbps CML input.
RX_REF_CK_P
RX_REF_CK_N
LVPECL/CML 155/622 MHz reference clock for RX. See
Figure 7.
REF_CK_N²
REF_CK_P
Transmitter reference clock input, see Figure 7. REF_CK is the
CMU reference clock.
TX_CK_LV_N, TX_CK_LV_P
LVDS TX clock, 622 MHz/311 MHz selectable, phase
adjustable.
TX_D_LV_N[15], TX_D_LV_P[15] LVDS data input. See Figure 8.
TX_D_LV_N[14], TX_D_LV_P[14]
TX_D_LV_N[13], TX_D_LV_P[13]
TX_D_LV_N[12], TX_D_LV_P[12]
TX_D_LV_N[11], TX_D_LV_P[11]
TX_D_LV_N[10], TX_D_LV_P[10]
TX_D_LV_N[9], TX_D_LV_P[9]
TX_D_LV_N[8], TX_D_LV_P[8]
TX_D_LV_N[7], TX_D_LV_P[7]
TX_D_LV_N[6], TX_D_LV_P[6]
TX_D_LV_N[5], TX_D_LV_P[5]
TX_D_LV_N[4], TX_D_LV_P[4]
TX_D_LV_N[3], TX_D_LV_P[3]
TX_D_LV_N[2], TX_D_LV_P[2]
TX_D_LV_N[1], TX_D_LV_P[1]
TX_D_LV_N[0], TX_D_LV_P[0]
RX_FILT_EXTP
RX_FILT_EXTN
RX External Filter. See Figure 9.
TX_FILT_EXTP
TX_FILT_EXTN
TX External Filter. See Figure 9.
RX_REF_CK_Enb
RX reference clock enable.
RX_LV_CKDLY[0]
RX_LV_CKDLY[1]
LVDS output clock delay programming.
SC_LV_ISET[0]
SC_LV_ISET[1]
LVDS output current settings.
RX_LOS
RX loss of signal. When RX_LOS is asserted, LVDS clock
RX_CK_LV_P/N is driven out, and the LVDS data pins are
muted (i.e. at differential 0).
RX_LOS_POL
RX lose signal polarity change.
RX_D_RP_Enb
Receive data repeater enable.
RX_LOCK2REFb
RX PLL lock to reference. The RX PLL locks to the recovered
data clock when this pin is unconnected/pulled high. The RX
PLL locks to either RX_REF_CK or REF_CK depending on the
state of RX_REF_CK_ENb.
SC_LOCK_DIFF[1]
SC_LOCK_DIFF[0]
Lock indicate frequency resolution settings.
RESET_TXb
Transmitter reset.
LB_P622_Enb
Loopback enabled at parallel 622 MHz port.
LB_LVDS_Enb
Loopback of TX 16b LVDS to RX 16b LVDS.
TX_FIFO_INIT
FIFO initialization.
SC_LSB1STb
SERDES LSB 1 first out selection.
TX_CML_ISET[1]
TX_CML_ISET[0]
CML output current settings.
Function
CML/In
CML/In or
LVPECL/In
CML/In
CML/In
LVDS/In
Flip-chip
BGA
Ball #
L15, K15
E17
D17
N1
P1
B9, A9
LVDS/In
Analog
Analog
LVCMOS/In
LVCMOS/In
LVCMOS/In
LVCMOS/In
B17, A17
B16, A16
B15, A15
B14, A14
B13, A13
B12, A12
B11, A11
B10, A10
B8, A8
B7, A7
B6, A6
B5, A5
B4, A4
B3, A3
B2, A2
B1, A1
D15
E15
M4
N4
M14
P13
R13
R16
R17
G12
LVCMOS/In
R7
LVCMOS/In
H11
LVCMOS/In
F11
LVCMOS/In
N13
N15
LVCMOS/In
F9
LVCMOS/In
E12
LVCMOS/In
C13
LVCMOS/In
D3
LVCMOS/In
F2
LVCMOS/In
J5
J1
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