XPIO110GXS Datasheet, PDF (3/23 Pages) Lattice Semiconductor – Fully Integrated 10Gbps Serializer/Deserializer Device

Lattice Semiconductor
XPIO 110GXS Data Sheet
The XPIO 110GXS is divided into a transmitter section and a receiver section. The major operations performed by
the chip are:
Transmitter Operation
1. Low jitter clock generation via the Clock-Multiplier-Unit (CMU)
2. 16-bit LVDS parallel data input
3. Parallel-to-serial conversion
10Gbps CML serial data output
Receiver Operation
1. CML serial input to a limiting amplifier
2. Clock and data recovery
3. Serial-to-parallel conversion
4. 16-bit LVDS parallel data output, with a synchronizing clock output
5. Built-in LVDS line loopback, and LVDS diagnostic loopback modes for testing and network diagnosis
Functional Description
The XPIO 110GXS transceiver is a low power, low jitter, and fully integrated serializer/deserializer chip. It operates
in the data rate range of 9.95-10.31 Gbps, performs all necessary parallel-to-serial and serial-to-parallel conver-
sions. The chip is suitable for applications utilizing OC-192 and 10GE. The serial interface I/O uses the CML stan-
dard while the low speed parallel I/O is based on the LVDS standard. These standards are compliant to both the
Optical Interface Forum's SFI-4 standard and the 10GE’s XSBI standard. The LVDS parallel I/O can be directly
connected to Multi-Standard-Agreement (MSA) 300 systems.
To accommodate bit order differences between OC-192 and 10GE, the XPIO 110GXS provides the capability of bit
swapping. The data presented on TX_D_LV_P/N[15] or MSB is transmitted first, followed in order by
TX_D_LV_P/N[14] to TX_D_LV_P/N[0] when SC_LSB1STb is not connected or is connected to a logic high.
TX_D_LV_P/N[0] or LSB is transmitted first followed in order by TX_D_LV_P/N[1] to TX_D_LV_P/N[15] when
SC_LSB1STb is connected to a logic low. The parallel receive bus mirrors this behavior. The SC_LSB1STb uncon-
nected, or at logic high, the first serial bit received is presented on RX_D_LV_P/N[15]. Conversely the first bit
received is presented on RX_D_LV_P/N[0] when SC_LSB1STb is pulled low.
Transmitter
The transmitter performs the serialization process, converting the 16-bit parallel LVDS data stream to a serial data
stream at approximately a 10 Gbps data rate. The transmitter consists of a LVDS data receiver, a FIFO, a 16:1 seri-
alizer, a low jitter CMU, and a 10Gbps output data driver.
LVDS Data Receiver
The Input and Analog Pin Assignments and Descriptions table in this document shows the 16 LVDS differential
data input pairs (TX_D_LV_P/N [15:0]). Data applied at the transmit data pairs is aligned to the LVDS input clock
(TX_CK_LV_P/N), which can be either 1/16th or 1/32nd the transmit data rate (622.08 or 311.04 nominally for OC-
192). The clock rate is selected through the assertion or deassertion of the TX_CK_LV_SEL pin. Figure 13
describes the LVDS data relationship to the LVDS input clock.
The LVDS input receivers convert the LVDS signals to CMOS signals. The converted signals are latched based on
an internal clock that is generated from the TX_CK_LV_P/N input clock through a phase-lock-loop (LVPLL). In
order to achieve optimal latch timing, the phase relationship between the internal clock and the TX_CK_LV_P/N
clock can be adjusted by programming TX_CK_LV_PA[1:0]. The LVDS PLL can also be bypassed by the assertion
of the TX_LV_PLLBPb pin, which is a desirable feature in some applications. When the LVPLL is bypassed it is up
to the system designer to manage the TX_CK_LV_P/N input.
Transmitter FIFO
A 16 bit wide and 8-word deep FIFO is designed into the XPIO 110GXS to decouple the LVDS clock from the serial
transmission clock. In addition, the FIFO also improves the tolerance to minor phase differences between the FIFO
write clock and read clock due to phase drift or phase wander.
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