IS61WV12816DALL_11 Datasheet, PDF (9/21 Pages) Integrated Silicon Solution, Inc – 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol
Parameter
-8
Min. Max.
-10
Min. Max.
-12
1
Min. Max.
Unit
tRC
Read Cycle Time
8—
10 —
12 —
ns
tAA
Address Access Time
tOHA
Output Hold Time
—8
2.0 —
— 10
2.0 —
— 12
ns
2
3—
ns
tACE
CE Access Time
—8
— 10
— 12
ns
tDOE
tHZOE⁽²⁾
OE Access Time
OE to High-Z Output
— 5.5
—3
— 6.0
—4
— 6.0
ns
—6
ns
3
tLZOE⁽²⁾
OE to Low-Z Output
0—
0—
0—
ns
tHZCE⁽²
tLZCE⁽²⁾
CE to High-Z Output
CE to Low-Z Output
03
3—
04
3—
06
ns
3—
ns
4
tBA
LB, UB Access Time
— 5.5
— 6.5
— 6.5
ns
tHZB⁽²⁾
tLZB⁽²⁾
LB, UB to High-Z Output
LB, UB to Low-Z Output
0 5.5
0—
0 6.5
0—
0 6.5
ns
0—
ns
5
tPU
Power Up Time
0—
0—
0—
ns
tPD
Notes:
Power Down Time
—8
— 10
— 10
ns
6
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. D
06/21/2011