IS61WV12816DALL_11 Datasheet, PDF (14/21 Pages) Integrated Silicon Solution, Inc – 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) ^{(1 )}
ADDRESS
CE
WE
UB, LB
DOUT
DIN
t SA
t WC
VALID ADDRESS
t SCE
t HA
t AW
t PWE1
t PWE2
t PBW
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) ^(1,2)
ADDRESS
OE
t WC
VALID ADDRESS
t HA
CE LOW
WE
UB, LB
t SA
DOUT
DATA UNDEFINED
DIN
t AW
t PWE1
t PBW
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
UB_CEWR2.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
06/21/2011