IS61WV12816DALL_11 Datasheet, PDF (10/21 Pages) Integrated Silicon Solution, Inc – 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
-20 ns
Min. Max.
-25 ns
Min. Max.
-35 ns
-45 ns
Min. Max.
Min. Max.
Unit
tRC
Read Cycle Time
20 —
25 —
35 —
45 —
ns
tAA
Address Access Time
— 20
— 25
— 35
— 45
ns
tOHA
Output Hold Time
2.5 —
6—
8—
10 —
ns
tACE
CE Access Time
— 20
— 25
— 35
— 45
ns
tDOE
OE Access Time
—8
— 12
— 15
— 20
ns
tHZOE⁽²⁾
OE to High-Z Output
08
08
0 10
0
15
ns
tLZOE⁽²⁾
OE to Low-Z Output
0—
0—
0—
0
—
ns
tHZCE⁽²
CE to High-Z Output
08
08
0 10
0
15
ns
tLZCE⁽²⁾
CE to Low-Z Output
3—
10 —
10 —
10 —
ns
tBA
LB, UB Access Time
—8
— 25
— 35
— 45
ns
tHZB
LB, UB to High-Z Output
08
08
0 10
0
15
ns
tLZB
LB, UB to Low-Z Output
0—
0—
0—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
06/21/2011