IS61WV12816DALL_11 Datasheet, PDF (15/21 Pages) Integrated Silicon Solution, Inc – 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) ⁽¹⁾
1
t WC
ADDRESS
VALID ADDRESS
2
OE LOW
t HA
CE _LOW
t AW
3
t PWE2
WE
t SA
t PBW
UB, LB
4
t HZWE
t LZWE
DOUT
DATA UNDEFINED
HIGH-Z
DIN
t SD
t HD
DATAIN VALID
5
UB_CEWR3.eps
6
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) ^(1,3)
ADDRESS
OE
CE _LOW
t WC
ADDRESS 1
t SA
WE
UB, LB
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t WC
ADDRESS 2
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
7
8
9
10
11
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
12
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. D
06/21/2011