IS61WV12816DALL_11 Datasheet, PDF (12/21 Pages) Integrated Silicon Solution, Inc – 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPWB
tPWE1
tPWE2
tSD
tHD
tHZWE⁽²⁾
tLZWE⁽²⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-8
Min. Max.
8—
6.5 —
6.5 —
0—
0—
6.5 —
6.5 —
8.0 —
5—
0—
— 3.5
2—
-10
Min. Max.
10 —
8—
8—
0—
0—
8—
8—
10 —
6—
0—
—5
2—
-12
Min. Max. Unit
12 —
ns
9—
ns
9—
ns
0—
ns
0—
ns
9—
ns
9—
ns
11 —
ns
9—
ns
0—
ns
—6
ns
3—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write. Shaded area product in development
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
06/21/2011