IS61WV12816DALL_11 Datasheet, PDF (13/21 Pages) Integrated Silicon Solution, Inc – 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPWB
tPWE1
tPWE2
tSD
tHD
tHZWE⁽³⁾
tLZWE⁽³⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-20 ns
Min. Max.
20 —
12 —
12 —
0—
0—
12 —
12 —
17 —
9—
0—
—9
3—
-25 ns
Min. Max.
25 —
18 —
15 —
0—
0—
18 —
18 —
20 —
12 —
0—
— 12
5—
-35 ns
Min. Max.
35 —
25 —
25 —
0—
0—
30 —
30 —
30 —
15 —
0—
— 20
5—
1 ^-45ns
Min. Max. Unit
45 —
ns
35 —
35 —
ns
2 ^ns
0—
0—
35 —
35 —
35 —
20 —
0—
— 20
5—
ns
3 ^ns
ns
ns
4 ^ns
ns
ns
5 ^ns
ns
Notes:
1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input
pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a.
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2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
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Integrated Silicon Solution, Inc. — www.issi.com
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Rev. D
06/21/2011