IS61NVVP25672 Datasheet, PDF (7/29 Pages) Integrated Silicon Solution, Inc – 256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

IS61NVVP25672
IS61NVVP51236
ISSI ^®
WRITE TRUTH TABLE (x72)
Operation
WE
BWa BWb BWc BWd
READ
H
X
X
X
X
WRITE BYTE a
L
L
H
H
H
WRITE BYTE b
L
H
L
H
H
WRITE BYTE c
L
H
H
L
H
WRITE BYTE d
L
H
H
H
L
WRITE BYTE e
L
H
H
H
H
WRITE BYTE f
L
H
H
H
H
WRITE BYTE g
L
H
H
H
H
WRITE BYTE h
L
H
H
H
H
WRITE ALL BYTEs
L
L
L
L
L
WRITE ABORT/NOP
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
BWe
X
H
H
H
H
L
H
H
H
L
H
BWf
X
H
H
H
H
H
L
H
H
L
H
BWg
X
H
H
H
H
H
H
L
H
L
H
BWh
X
H
H
H
H
H
H
H
L
L
H
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
ADVANCED INFORMATION Rev. 00A
07/17/02