IS61NVVP25672 Datasheet, PDF (20/29 Pages) Integrated Silicon Solution, Inc – 256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

IS61NVVP25672
IS61NVVP51236
ISSI ^®
IDENTIFICATION (ID) REGISTER
The ID Register is a 32-bit register that is loaded with a
device and vendor specific 32-bit code when the controller
is put in Capture-DR state with the IDCODE command
loaded in the Instruction Register. The code is loaded from
a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed
between the TDI and TDO pins when the controller is moved
into Shift-DR state. Bit 0 in the register is the LSB and the
first to reach TDO when shifting begins.
ID REGISTER CONTENTS
Die
Revision
Code
Not Used
I/O
Configuration
ISSI Technology
JEDEC Vendor
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1
x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1
20
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00A
07/17/02