IS61NVVP25672 Datasheet, PDF (6/29 Pages) Integrated Silicon Solution, Inc – 256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

IS61NVVP25672
IS61NVVP51236
ASYNCHRONOUS TRUTH TABLE⁽¹⁾
Operation
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
L
L
H
DQ
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE,
otherwise data bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle
time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x36)
Operation
WE
BWa BWb BWc BWd
READ
H
X
X
X
X
WRITE BYTE a
L
L
H
H
H
WRITE BYTE b
L
H
L
H
H
WRITE BYTE c
L
H
H
L
H
WRITE BYTE d
L
H
H
H
L
WRITE ALL BYTEs
L
L
L
L
L
WRITE ABORT/NOP
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
ISSI ^®
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00A
07/17/02