IS61NVVP25672 Datasheet, PDF (22/29 Pages) Integrated Silicon Solution, Inc – 256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

IS61NVVP25672
IS61NVVP51236
ISSI ^®
JTAG TAP INSTRUCTION SET SUMMARY
Instruction
Code
Description
EXTEST⁽¹⁾
000
Places the Boundary Scan Register between TDI and TDO. When EXTEST is
selected, data will be driven out of the DQ pad.
IDCODE^(1,2)
001
Preloads ID Register and places it between TDI and TDO.
SAMPLE-Z⁽¹⁾
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI
and TDO. Forces all Data and Clock output drivers to High-Z.
RFU⁽¹⁾
011
Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruc-
tion. Places Bypass Register between TDI and TDO.
SAMPLE/PRELOAD⁽¹⁾ 100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Private⁽¹⁾
101
Private instruction.
RFU⁽¹⁾
110
Do not use this instruction; Reserved for Future Use.
BYPASS⁽¹⁾
111
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state.
TAP ELECTRICAL CHARACTERISTICS Over the Operating Range^(1,2)
Symbol
Parameter
Test Conditions
VOH1
Output HIGH Voltage
IOH = –100 µA
VOH2
Output HIGH Voltage
IOH = –8 mA
VOL1
Output LOW Voltage
IOL = 100 µA
VOL2
Output LOW Voltage
IOL = 8 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOLT = 2mA
IX
Input Leakage Current
GND ≤ V I ≤ VDDQ
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
Undershoot:VIL (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
Min.
Max.
Vcc –0.1 —
Vcc –0.4 —
—
0.1
—
0.4
1.2 VCC +0.3
–0.3
0.6
–10
10
Units
V
V
V
V
V
V
µA
22
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00A
07/17/02