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IS61NVVP25672 Datasheet, PDF (15/29 Pages) Integrated Silicon Solution, Inc – 256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVP25672
IS61NVVP51236
SINGLE READ/WRITE CYCLE TIMING
Clock
CKE
tSE tHE
Address
A1
A2
A3
WRITE
CS
A4
A5
A6
A7
ADV
OE
Data Out
Data In
tOEQ
tOELZ
Q1
Q3
tDS tDH
D2
NOTES: WRITE = L means WE = L and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
Q4
D5
ISSI ®
tKH
tKL
tKC
A8
A9
Q6
Q7
Don't Care
Undefined
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
15
ADVANCED INFORMATION Rev. 00A
07/17/02