IS61NVVP25672 Datasheet, PDF (4/29 Pages) Integrated Silicon Solution, Inc – 256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

IS61NVVP25672
IS61NVVP51236
PIN CONFIGURATION
119-pin PBGA (Top View)
1
2
3
4
A
VCCQ
A
A
A
B
NC
CE2
A
ADV
C
NC
A
A
VCC
D
DQc
DQPc GND
NC
E
DQc
DQc
GND
CE
F
VCCQ DQc
GND
OE
G
DQc
DQc
BWc
A
H
DQc
DQc
GND
WE
J
VCCQ VCC
NC
VCC
K
DQd
DQd
GND
CLK
L
DQd
DQd
BWd
NC
M
VCCQ
DQd
GND
CKE
N
DQd
DQd
GND
A1
P
DQd
DQPd GND
A0
R
NC
A
MODE VCC
T
NC
NC
A
A
U
VCCQ TMS
TDI
TCK
5
6
7
A
A
A
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A
TDO
A
CE2
VCCQ
NC
A
NC
DQPb DQb
DQb
DQb
DQb VCCQ
DQb
DQb
DQb
DQb
VCC VCCQ
DQa
DQa
DQa
DQa
DQa VCCQ
DQa
DQa
DQPa DQa
A
NC
NC
ZZ
NC
VCCQ
512K x 36
ISSI ^®
PIN DESCRIPTIONS
A
Synchronous Address Inputs
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
ADV
Synchronous Burst Address Advance
BWa-BWh
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK
CKE
Synchronous Clock
Clock Enable
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd Parity Data Input/Output
GND
MODE
OE
TCK, TDI
TDO, TMS
VCC
VCCQ
WE
ZZ
Ground
Burst Sequence Mode Selection
Output Enable
JTAG Boundary Scan Pins
1.8V Power Supply
Isolated Output Buffer Supply: 1.8V
Write Enable
Snooze Enable
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00A
07/17/02