IS61NVVP25672 Datasheet, PDF (23/29 Pages) Integrated Silicon Solution, Inc – 256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

IS61NVVP25672
IS61NVVP51236
ISSI ^®
TAP AC ELECTRICAL CHARACTERISTICS⁽¹⁾ (OVER OPERATING RANGE)
Symbol Parameter
Min.
tTCYC TCK Clock cycle time
100
fTF
TCK Clock frequency
—
tTH
TCK Clock HIGH
40
tTL
TCK Clock LOW
40
tTMSS TMS setup to TCK Clock Rise
10
tTDIS
TDI setup to TCK Clock Rise
10
tCS
Capture setup to TCK Rise
10
tTMSH TMS hold after TCK Clock Rise
10
tTDIH
TDI Hold after Clock Rise
10
tCH
Capture hold after Clock Rise
10
tTDOV TCK LOW to TDO valid
—
tTDOX TCK LOW to TDO invalid
0
Notes:
7. tCS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register.
8. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Max.
—
10
—
—
—
—
—
—
—
—
20
—
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
1
Run Test/Idle
0
1
Select DR
0
1 _{Capture DR}
0
Shift DR
1
0
Exit1 DR ¹
0
Pause DR
1
0
0 ^{Exit2 DR}
1
1
Update DR
0
1
Select IR
0
1 _{Capture IR}
0
Shift IR
10
Exit1 IR ¹
0
Pause IR
1
0
0 ^{Exit2 IR}
1
1
Update IR
0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
23
ADVANCED INFORMATION Rev. 00A
07/17/02