IS61LPS51218A_12 Datasheet, PDF (7/35 Pages) Integrated Silicon Solution, Inc – 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 PBGA PACKAGE PIN CONFIGURATION
512K x 18 (TOP VIEW)
1
A
NC
B
NC
C
NC
D
NC
E
NC
F
NC
G
NC
H
NC
J
DQb
K
DQb
L
DQb
M DQb
N DQPb
P
NC
R MODE
2
A
A
NC
DQb
DQb
DQb
DQb
Vss
NC
NC
NC
NC
NC
NC
NC
3
CE
CE2
Vddq
Vddq
Vddq
Vddq
Vddq
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
A
4
BWb
NC
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
A
5
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDI
TMS
6
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A1*
A0*
7
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDO
TCK
8
ADSC
OE
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
A
9
ADV
ADSP
Vddq
Vddq
Vddq
Vddq
Vddq
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQx
DQPx
Vdd
Vddq
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc.
7
Rev. L
09/06/12