IS61LPS51218A_12 Datasheet, PDF (17/35 Pages) Integrated Silicon Solution, Inc – 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-250 -200 -166
Symbol Parameter
Min. Max. Min. Max. Min. Max.
Unit
fmax
Clock Frequency
— 250
— 200
— 166
MHz
tkc
Cycle Time
4.0 —
5—
6—
ns
tkh
Clock High Time
1.7 —
2—
2.4 —
ns
tkl
Clock Low Time
1.7 —
2—
2.3 —
ns
tkq
Clock Access Time
— 2.6
— 3.1
— 3.8
ns
tkqx⁽²⁾ Clock High to Output Invalid
0.8 —
1.5 —
1.5 —
ns
tkqlz^(2,3) Clock High to Output Low-Z
0.8 —
1—
1.5 —
ns
tkqhz^(2,3) Clock High to Output High-Z
— 2.6
— 3.0
3.5 —
ns
toeq
Output Enable to Output Valid
— 2.6
— 3.1
3.5 —
ns
toelz^(2,3) Output Enable to Output Low-Z
0
—
0—
0—
ns
toehz^(2,3) Output Disable to Output High-Z
— 2.6
— 3.0
3.5 —
ns
tas
Address Setup Time
1.2 —
1.4 —
1.7 —
ns
tws
Read/Write Setup Time
1.2 —
1.4 —
1.7 —
ns
tces
Chip Enable Setup Time
1.2 —
1.4 —
1.7 —
ns
tavs
Address Advance Setup Time
1.2 —
1.4 —
1.7 —
ns
tds
Data Setup Time
1.2 —
1.4 —
1.7 —
ns
tah
Address Hold Time
0.3 —
0.4 —
0.7 —
ns
twh
Write Hold Time
0.3 —
0.4 —
0.7 —
ns
tceh
Chip Enable Hold Time
0.3 —
0.4 —
0.7 —
ns
tavh
Address Advance Hold Time
0.3 —
0.4 —
0.7 —
ns
tdh
Data Hold Time
0.3 —
0.4 —
0.7 —
ns
tpds
ZZ High to Power Down
—
2
—2
—2
cyc
tpus
ZZ Low to Power Down
—
2
—2
—2
cyc
Note:
1.Configuration signal MODE is static and must not change during normal operation.
2.Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc.
17
Rev. L
09/06/12