IS61LPS51218A_12 Datasheet, PDF (15/35 Pages) Integrated Silicon Solution, Inc – 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
CAPACITANCE^(1,2)
Symbol Parameter
Conditions
Max.
Cin
Input Capacitance
Vin = 0V
6
Cout
Input/Output Capacitance
Vout = 0V
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Unit
pF
pF
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
and Refe rence Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
ZO = 50Ω
Output
Figure 1
50Ω
1.5V
3.3V
317 Ω
OUTPUT
5 pF
Including
jig and
scope
Figure 2
351 Ω
Integrated Silicon Solution, Inc.
15
Rev. L
09/06/12