IS61LPS51218A_12 Datasheet, PDF (4/35 Pages) Integrated Silicon Solution, Inc – 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
119 BGA PACKAGE PIN CONFIGURATION-256K x 36 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
B
NC
CE2
A
ADSC
A
A
VDDQ
A
NC
C
NC
A
A
VDD
A
A
NC
D
DQc DQPc
Vss
E
DQc DQc
Vss
F
VDDQ
DQc
Vss
G
DQc DQc
BWc
H
DQc DQc
Vss
NC
CE
OE
ADV
GW
Vss
Vss
Vss
BWb
Vss
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
VDDQ
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd DQd
Vss
CLK
Vss
DQa DQa
L
DQd DQd
BWd
NC
BWa
DQa DQa
M
VDDQ
DQd
Vss
BWE
Vss
DQa
VDDQ
N
DQd DQd
Vss
A1*
Vss
DQa DQa
P
DQd DQPd
Vss
A0*
Vss
DQPa DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
A0, A1
ADV
ADSP
ADSC
GW
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
CLK
CE, CE2
Synchronous Clock
Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Controls
BWE
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQd
DQPa-Pd
Vdd
Vddq
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
4
Integrated Silicon Solution, Inc.
Rev. L
09/06/12