IS61LPS51218A_12 Datasheet, PDF (6/35 Pages) Integrated Silicon Solution, Inc – 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
165 PBGA PACKAGE PIN CONFIGURATION
256K x 36 (TOP VIEW)
1
2
3
4
5
A
NC
A
CE
BWc
BWb
B
NC
A
CE2
BWd
BWa
C
DQPc
NC
Vddq
Vss
Vss
D
DQc
DQc
Vddq
Vdd
Vss
E
DQc
DQc
Vddq
Vdd
Vss
F
DQc
DQc
Vddq
Vdd
Vss
G
DQc
DQc
Vddq
Vdd
Vss
H
NC
Vss
NC
Vdd
Vss
J
DQd
DQd
Vddq
Vdd
Vss
K
DQd
DQd
Vddq
Vdd
Vss
L
DQd
DQd
Vddq
Vdd
Vss
M
DQd
DQd
Vddq
Vdd
Vss
N
DQPd
NC
Vddq
Vss
NC
P
NC
NC
A
A
TDI
R
MODE
NC
A
A
TMS
6
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A1*
A0*
7
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
TDO
TCK
8
ADSC
OE
Vss
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vss
A
A
9
ADV
ADSP
Vddq
Vddq
Vddq
Vddq
Vddq
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
A
A
PIN DESCRIPTIONS
Symbol
A
Pin Name
Address Inputs
A0, A1
ADV
ADSP
ADSC
GW
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
CLK
Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx (x=a,b,c,d) Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQx
DQPx
Vdd
Vddq
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V/2.5V
Ground
6
Integrated Silicon Solution, Inc.
Rev. L
09/06/12